Abstract: The present application discloses a display device capable of performing favorable display in which flicker is not visually recognized while the power consumption of a scanning-side drive circuit, as well as a data-side drive circuit, can be reduced sufficiently when pause driving is performed. A pixel circuit including emission control transistors M5, M6 in addition to a drive transistor M1 includes a switching element that is turned on based on a voltage of an emission control line Ei to initialize an organic EL element OL when the voltage of the emission control line Ei is at a level for turning off the emission control transistors M5, M6. For example, in some embodiments, the anode electrode of the organic EL element OL is connected to an initialization voltage line Vini via an N-channel transistor M7 serving as the switching element, and the emission control line Ei is connected to the gate terminal of the transistor M7.

Abstract: With respect to a display device having an external compensation function, a monitor time can be shortened without increasing the number of wiring lines. A pixel circuit in an i-th row and a j-th column includes an organic EL element (display element), a writing control transistor, a drive transistor, a monitor control transistor, and a holding capacitor. A control terminal of the drive transistor is connected to a data signal line S(j) in the j-th column via the write control transistor. The monitor control transistor includes a first conduction terminal connected to a second conduction terminal of the drive transistor, and a second conduction terminal connected to a data signal line S(j+1) in a (j+1)-th column.

Abstract: A display device includes a display control circuit configured to control a data-side drive circuit and a scanning-side drive circuit such that a drive period and a pause period alternate between one another. The display control circuit, in the pause period, such that voltage of corresponding data signal line is applied to first conduction terminal of drive transistor as bias voltage when light emission control transistor is in an off state and current corresponding to holding voltage of holding capacitor flows through display element when light emission control transistor is in an on state, causes the data-side drive circuit to output the bias voltage and apply the bias voltage to data signal lines and causes the scanning-side drive circuit to stop driving first scanning signal lines and selectively drive second scanning signal lines and selectively make light emission control lines inactive.

Abstract: The present application discloses a display device capable of performing favorable display in which flicker is not visually recognized while the power consumption of a scanning-side drive circuit, as well as a data-side drive circuit, can be reduced sufficiently when pause driving is performed. A pixel circuit including emission control transistors M5, M6 in addition to a drive transistor M1 includes a switching element that is turned on based on a voltage of an emission control line Ei to initialize an organic EL element OL when the voltage of the emission control line Ei is at a level for turning off the emission control transistors M5, M6. For example, in some embodiments, the anode electrode of the organic EL element OL is connected to an initialization voltage line Vini via an N-channel transistor M7 serving as the switching element, and the emission control line Ei is connected to the gate terminal of the transistor M7.

Abstract: A pixel circuit for a display device is disclosed. The pixel circuit may include a drive transistor configured to control an amount of current from a first power supply to a light-emitting device depending upon a voltage applied to a gate of the drive transistor. The light-emitting device includes a first terminal electrically connected to a second terminal of the drive transistor and a second terminal electrically connected to a second power supply. The pixel circuit may also include a storage capacitor including a first plate connected to the gate terminal of the drive transistor and a second plate connected to a first node. The pixel circuit may also include a plurality of transistors configured to couple the first power supply, a data voltage input line, and a preset voltage input line to the pixel circuit.

Abstract: A display device includes: a display unit including a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, and a plurality of pixel circuits; and a drive circuit configured to drive the first scan lines, the second scan lines, and the data lines. Each of the pixel circuits includes: a light-emitting element; a drive transistor configured to control a magnitude of an electric current that flows through the light-emitting element, the drive transistor being of a first conductivity type; a first compensation transistor having a control terminal connected to an associated one of the first scan lines, the first compensation transistor being of the first conductivity type; and a second compensation transistor having a control terminal connected to an associated one of the second scan lines, the second compensation transistor being of a second conductivity type.

Abstract: With respect to a display device having an external compensation function, a monitor time can be shortened without increasing the number of wiring lines. A pixel circuit in an i-th row and a j-th column includes an organic EL element (display element), a writing control transistor, a drive transistor, a monitor control transistor, and a holding capacitor. A control terminal of the drive transistor is connected to a data signal line S(j) in the j-th column via the write control transistor. The monitor control transistor includes a first conduction terminal connected to a second conduction terminal of the drive transistor, and a second conduction terminal connected to a data signal line S(j+1) in a (j+1)-th column.

Abstract: A pixel circuit includes a drive transistor configured to control an amount of current to a light emitting device during an emission phase depending upon a voltage applied to a control terminal of the drive transistor, the drive transistor having a first terminal and a second terminal. During a first phase, an anode of the light emitting device is set to a reference voltage and the first terminal of the drive transistor is set to a fixed data voltage such that the drive transistor is stressed with a fixed source-to-gate voltage to prevent a drift of a threshold voltage in the drive transistor thereby preventing a drift in screen brightness. During a second phase, the anode of the light emitting device is set to the reference voltage and the first terminal of the drive transistor is set to a voltage of the first power supply.

Abstract: A liquid crystal display device includes an active matrix substrate, a counter substrate, and a liquid crystal layer. The active matrix substrate includes a top gate type oxide semiconductor TFT a plurality of gate wiring lines a plurality of source and an interlayer insulating layer The counter substrate includes a plurality of columnar spacers provided on a second substrate. Each columnar spacer is disposed in an intersecting region where the gate wiring line and the source wiring line intersect. A front face of the active matrix substrate on the liquid crystal layer side includes a plurality of first ridges overlapping the plurality of gate wiring lines and a plurality of second ridges overlapping the plurality of source wiring lines.

Abstract: An enhanced pixel circuit for a display device provides separate compensation and data programming phases to permit minimization of the programming time. Variations in voltage supplies are accounted for by isolating the drive transistor from such power supply by using a second drive transistor configured as source follower relative to the first drive transistor. An on bias stress transistor is incorporated that can electrically connect the first drive transistor to the power supply during an on bias stress operation. During such operation, a voltage stress is applied to eliminate hysteresis effects associated with the drive transistor. The on bias stress operation may be performed as part of a refresh operation during which a data voltage is programmed to the pixel circuit, or as part of a low frequency operation during which a previously programming data voltage is maintained which reduces power consumption.

Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer.

Abstract: A display device includes: an active matrix substrate including pixels arrayed in a matrix shape including rows and columns, and scanning wiring lines extending in a row direction and signal wiring lines extending in a column direction, wherein the active matrix substrate includes, in each of pixels, a TFT, a pixel electrode formed of a transparent conductive material and electrically connected to the TFT, a color filter located between the TFT and the pixel electrode, and a connecting electrode formed of a transparent conductive material and electrically connecting the TFT to the pixel electrode, the color filter includes a first color filter layer provided on the TFT and including a first contact hole, and a second color filter layer provided on the first color filter layer and including a second contact hole, and the first contact hole and the second contact hole do not overlap with each other.

Abstract: An active matrix substrate 10 configuring the display panel includes a plurality of gate lines provided in each of pixel segments Snm arrayed in a matrix form, and a plurality of data lines crossing the gate lines. The pixel segments Snm are provided respectively with gate line drive circuitry 13. Each of the gate line drive circuitry 13 is connected to drive control lines 152 and 153 that are supplied with drive control signals Sxm and Sym commanding drive or stop of the gate line drive circuitry. The gate line drive circuitry 13 having received the drive control signal commanding drive scans the gate lines in the pixel segment including the gate line drive circuitry 13.

Abstract: Provide is a technique that enables to easily arrange driving circuits for driving gate lines within pixels, and to reduce display defects in a vertical stripe pattern. An active matrix substrate includes, in each pixel PIX, a pixel electrode 141, and a pixel switching element 10 that is connected with a gate line 13, a source line 15, and the pixel electrode 141. Driving circuit elements 110 of driving circuits for driving the gate lines 13 are arranged in a light-shielding area BM in a part of the pixels PIX in a display area. The pixel switching elements 10 in a row of the pixels in which the driving circuit element 110 is arranged are provided at non-uniform intervals, and drains of the pixel switching elements 10 in the same row are on the same side with respect to the source lines to which the pixel switching elements 10 are connected.

Abstract: In a display device, a pixel circuit includes a light-emitting element disposed between the first power source wiring line and the second power source wiring line, first and second conductive terminals of a first drive transistor and first and second conductive terminals of a switching control transistor which are disposed between the first power source wiring line and the second power source wiring line, and connected in series with the light-emitting element, and first and second conductive terminals of a second drive transistor which are disposed between the first power source wiring line and the second power source wiring line, connected in series with the light-emitting element, and connected in parallel with the first and second conductive terminals of the first drive transistor and the first and second conductive terminals of the switching control transistor.

Abstract: A liquid crystal display device includes an active matrix substrate, a counter substrate, and a liquid crystal layer. The active matrix substrate includes a top gate type oxide semiconductor TFT a plurality of gate wiring lines a plurality of source and an interlayer insulating layer The counter substrate includes a plurality of columnar spacers provided on a second substrate. Each columnar spacer is disposed in an intersecting region where the gate wiring line and the source wiring line intersect. A front face of the active matrix substrate on the liquid crystal layer side includes a plurality of first ridges overlapping the plurality of gate wiring lines and a plurality of second ridges overlapping the plurality of source wiring lines.

Abstract: Provided is a display device in which variation in white balance is suppressed even if wiring lines are arranged in pixels. The display device includes: gate lines; source lines 15S; drive elements connected to the gate lines and the source lines 15S; pixel electrodes connected to the drive elements; and color filters provided corresponding to the pixel electrodes. The pixel electrodes are provided in one-to-one correspondence with subpixels, and a plurality of subpixels 18R, 18G, and 18B constitute one pixel. The display device further includes wiring lines L provided in a pixel region so as to extend along either the gate lines or the source lines. At least some of the wiring lines L are arranged in pixel aperture regions of the subpixels 18. The arrangement pitch P1 of the wiring lines L is larger than the pixel pitch (3×Sa).

Abstract: Provided is a technique for decreasing the deterioration of the display quality, while reducing electric power consumption. An active matrix substrate includes a plurality of gate lines Gn, Gn+1, a plurality of source lines S, a plurality of pixels PIX that are provided with pixel electrodes 11, respectively, and pixel switching elements 12 each of which is connected with the pixel electrode 11, the gate line, and the source line. The pixel electrode 11 has a connection portion 11b to which the pixel switching element 12 is connected. The connection portion 11b extends to an adjacent one of the pixels that is adjacent to the pixel where the pixel electrode 11 is provided, in a gate line extending direction. A data signal supplied by a source line has a polarity that is opposite to a polarity of a data signal supplied by an source line adjacent to the source line, and that is inverted every vertical period.

Abstract: An active-matrix display device has a gate driver for driving a plurality of gate bus lines of a display portion in accordance with a multi-phase gate clock signal. The gate driver includes first and second gate drivers disposed to opposite sides of the display portion. Each of the first and second gate drivers includes a plurality of buffer circuits connected to the gate bus lines and a plurality of bistable circuits cascaded together so as to constitute a shift register. Each bistable circuit controls two buffer circuits. The bistable circuits are disposed in an interlaced arrangement between the first and second gate drivers. Each of the two buffer circuits controlled by each bistable circuit includes a boost capacitor, and one of the two buffer circuits includes a transistor for isolating a boost effect.

Abstract: Provided is an active matrix substrate 20a in which either a plurality of source lines (data lines) 15S or a plurality of gate lines 13G, as constituent elements of the active matrix substrate 20a, are vertical lines extending in the longitudinal direction, and the other are horizontal lines. Among a plurality of pixel control elements 16T that are provided in correspondence to a plurality of pixels and are connected with the data line 15S and the gate lines 13G so as to control display of the corresponding pixels, respectively, a part of the pixel control elements 16T connected with one same horizontal line are arranged on one side with respect to the respective vertical lines to which the pixel control elements are connected, the side being different from a side on which the other pixel control elements connected with the same horizontal line are arranged.