Patents by Inventor Kohichi Hayakawa

Kohichi Hayakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6919564
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: July 19, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Patent number: 6903821
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: June 7, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Patent number: 6759655
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa
  • Publication number: 20030058444
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: November 5, 2002
    Publication date: March 27, 2003
    Applicant: HITACHI, LTD.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Kohichi Hayakawa, Maki Ito
  • Patent number: 6493082
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20020113967
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 22, 2002
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20020109088
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 5, 2002
    Publication date: August 15, 2002
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20020105648
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 4, 2002
    Publication date: August 8, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Patent number: 6421122
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: July 16, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20010019411
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 6, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20010011706
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 9, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito