Patents by Inventor Kohichi NAGAMI

Kohichi NAGAMI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875881
    Abstract: At a first timing after mounting a semiconductor wafer W on an electrostatic chuck 38, a susceptor 12 is switched from an electrically grounded state into a floated state. From a second timing after the first timing, a second high frequency power HF for plasma generation is applied to the susceptor 12, and a processing gas is excited into plasma in a chamber 10. From a third timing after the second timing, a first high frequency power LF for ion attraction is applied to the susceptor 12, and a self-bias (?Vdc) is generated. From a fourth timing close to the third timing, a negative second DC voltage ?BDC corresponding to the self-bias (?Vdc) is applied to the susceptor 12. From the fifth timing after the fourth timing, a positive first DC voltage ADC is applied to an inner electrode 42 of the electrostatic chuck 38.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: January 23, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kohichi Nagami, Norikazu Yamada, Tadashi Gondai, Kouichi Yoshida
  • Publication number: 20140231389
    Abstract: At a first timing after mounting a semiconductor wafer W on an electrostatic chuck 38, a susceptor 12 is switched from an electrically grounded state into a floated state. From a second timing after the first timing, a second high frequency power HF for plasma generation is applied to the susceptor 12, and a processing gas is excited into plasma in a chamber 10. From a third timing after the second timing, a first high frequency power LF for ion attraction is applied to the susceptor 12, and a self-bias (?Vdc) is generated. From a fourth timing close to the third timing, a negative second DC voltage ?BDC corresponding to the self-bias (?Vdc) is applied to the susceptor 12. From the fifth timing after the fourth timing, a positive first DC voltage ADC is applied to an inner electrode 42 of the electrostatic chuck 38.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kohichi Nagami, Norikazu Yamada, Tadashi Gondai, Kouichi Yoshida
  • Patent number: 8438206
    Abstract: A linear feedback shift calculation apparatus, into which input data is input, and which outputs output data, including: an L generation unit which generates q values of q0 to qN?2 represented by: q k = { p 0 ( k = 0 ) p k + ? i = 0 k - 1 ? q k - 1 - i × p i ( 1 ? k ? N - 2 ) Equation ? ? 1 (where, p0, p1, . . . , pN?1, q0, q1, . . .
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: May 7, 2013
    Assignee: Fujitsu Limited
    Inventor: Kohichi Nagami
  • Publication number: 20100098148
    Abstract: A linear feedback shift calculation apparatus, into which input data is input, and which outputs output data, including: an L generation unit which generates q values of q0 to qN?2 represented by: q k = { p 0 ( k = 0 ) p k + ? i = 0 k - 1 ? q k - 1 - i × p i ( 1 ? k ? N - 2 ) Equation ? ? 1 (where, p0, p1, . . . , pN?1, q0, q1, . . .
    Type: Application
    Filed: October 2, 2009
    Publication date: April 22, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Kohichi NAGAMI