Patents by Inventor Kohichi Ohsumi

Kohichi Ohsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9928400
    Abstract: A wiring board for a fingerprint sensor includes a core insulating layer having a thickness of 30 ?m to 100 ?m, an inner buildup insulating layer having a thickness of 17 ?m to 35 ?m, an outer buildup insulating layer having a thickness of 7 ?m to 25 ?m, a plurality of fingerprint reading outer strip-shaped electrodes, a plurality of fingerprint reading inner strip-shaped electrodes, and an upper solder resist layer covering the outer strip-shaped electrodes by a thickness of 3 ?m to 15 ?m.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 27, 2018
    Assignee: KYOCERA CORPORATION
    Inventor: Kohichi Ohsumi
  • Publication number: 20170091511
    Abstract: A wiring board for a fingerprint sensor includes a core insulating layer having a thickness of 30 ?m to 100 ?m, an inner buildup insulating layer having a thickness of 17 ?m to 35 ?m, an outer buildup insulating layer having a thickness of 7 ?m to 25 ?m, a plurality of fingerprint reading outer strip-shaped electrodes, a plurality of fingerprint reading inner strip-shaped electrodes, and an upper solder resist layer covering the outer strip-shaped electrodes by a thickness of 3 ?m to 15 ?m.
    Type: Application
    Filed: September 21, 2016
    Publication date: March 30, 2017
    Applicant: KYOCERA Corporation
    Inventor: Kohichi OHSUMI
  • Publication number: 20150351257
    Abstract: A method for producing a wiring board includes the steps of forming an upper insulating layer on a lower insulating layer having a lower wiring conductor on its upper surface; forming a via-hole in the upper insulating layer; depositing a first base metal layer in the via-hole and on an upper surface of the upper insulating layer; forming a first plating resist layer on the first base metal layer; depositing a first electrolytically plated layer to completely fill at least the via-hole; forming a via conductor, and depositing a second base metal layer; forming a second plating resist layer on the second base metal layer; depositing a second electrolytically plated layer; and forming a wiring pattern.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 3, 2015
    Applicant: KYOCERA CIRCUIT SOLUTIONS, INC.
    Inventors: Kohichi OHSUMI, Kazuki OKA
  • Publication number: 20150027977
    Abstract: A manufacturing method includes a step of forming a first plating mask on a base metal layer, a step of forming a main conductor layer on the base metal layer exposed from the first plating mask, a step of forming a second plating mask on them, a step of attaching a metal plating layer to an upper surface of the main conductor layer exposed from the second plating mask, a step of removing the first and second plating masks, a step of etching away a portion of the base metal layer to which the main conductor layer is not attached, and a step of forming a solder resist layer.
    Type: Application
    Filed: July 25, 2014
    Publication date: January 29, 2015
    Applicant: KYOCERA SLC Technologies Corporation
    Inventors: Kohichi OHSUMI, Sumiko NOGUCHI
  • Publication number: 20140001637
    Abstract: A wiring board in which a semiconductor element connection pad formed on a strip-shaped wiring conductor and an electrode of a semiconductor element are firmly connected together, the wiring board having excellent electrical insulation between the semiconductor element connection pads which are adjacent to each other.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 2, 2014
    Inventors: Kohichi OHSUMI, Yoshitaka SHIGA, Daichi OHMAE
  • Patent number: 8578601
    Abstract: A method of manufacturing a printed circuit board includes forming a through hole 2 in an insulating layer 1 having upper and lower faces so as to penetrate between the upper and lower surfaces; allowing a first plated conductor 4 to be deposited at least in the through hole 2 and on the upper and lower surfaces around the through hole; removing the first plated conductor overlying and underlying a periphery of the through hole by etching the first plated conductor 4, while leaving at least the first plated conductor 4 in a mid-portion in a vertical direction within the through hole 2; and forming by semi-additive method a second plated conductor 6 that fills an outer portion than the first plated conductor 4 in the through hole 2, and forms a wiring conductor on the upper and lower surfaces.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: November 12, 2013
    Assignee: Kyocera SLC Technologies Corporation
    Inventors: Kohichi Ohsumi, Kazunori Hayashi, Tomoharu Tsuchida
  • Patent number: 8319115
    Abstract: A wiring board includes a plurality of circular semiconductor element connection pads deposited in a lattice form onto a mounting portion of an insulation substrate, their upper surfaces being connected to electrodes of a semiconductor element. A solder resist layer is deposited onto the insulation substrate, which covers the side surfaces of these pads and exposes the upper surfaces of these pads. The solder resist layer has a concave part whose bottom surface corresponds to at least all the upper surfaces of these pads.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: November 27, 2012
    Assignee: Kyocera SLC Technologies Corporation
    Inventor: Kohichi Ohsumi
  • Patent number: 8304663
    Abstract: In a wiring board, insulation layers and wiring conductors are alternately laminated, and a plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged side by side on the outermost insulation layer. Each of the wiring conductors partly has a connection pad to which the electrode terminals of the semiconductor elements are connected by flip-chip bonding. In the wiring board, a solder resist layer is deposited over the outermost insulation layer and the strip-shaped wiring conductors so as to have slit-shaped openings for exposing the upper surfaces of the connection pads. The solder resist layer fills up the space between the connection pads adjacent to each other and exposed within the slit-shaped openings.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: November 6, 2012
    Assignee: KYOCERA SLC Technologies Corporation
    Inventor: Kohichi Ohsumi
  • Publication number: 20120145665
    Abstract: A method of manufacturing a printed circuit board includes forming a through hole 2 in an insulating layer 1 having upper and lower faces so as to penetrate between the upper and lower surfaces; allowing a first plated conductor 4 to be deposited at least in the through hole 2 and on the upper and lower surfaces around the through hole; removing the first plated conductor overlying and underlying a periphery of the through hole by etching the first plated conductor 4, while leaving at least the first plated conductor 4 in a mid-portion in a vertical direction within the through hole 2; and forming by semi-additive method a second plated conductor 6 that fills an outer portion than the first plated conductor 4 in the through hole 2, and forms a wiring conductor on the upper and lower surfaces.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 14, 2012
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventors: Kohichi OHSUMI, Kazunori HAYASHI, Tomoharu TSUCHIDA
  • Patent number: 7834277
    Abstract: The present invention provides a method of manufacturing printed a circuit board capable of formation of via holes having a low aspect ratio and formation of fine lines, and a printed circuit board manufactured by the method. The method of manufacturing a printed circuit board 10 according to the present invention includes a step of selectively forming a plating layer 16 for lands 22a and 22b on a metal foil 14 on the printed circuit board 10, a step of adjusting the thickness of the plating layer 16, and a step of forming the metal foil 14 into lines 14a. The aspect ratio of via holes 28 formed on lands 22a and 22b can be adjusted by adjusting the thickness of the lands 22a and 22b.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: November 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Ohsumi, Kenji Terada, Kohichi Yamazaki
  • Patent number: 7726016
    Abstract: The present invention provides a method of manufacturing a printed circuit board. The method includes the steps of preparing an insulating substrate having a front surface and a back surface and a layer of metal foil formed on each of the front surface and the back surface; selectively forming a plating layer for forming a land on at least one of the metal foils; adjusting a thickness of the plating layer; and forming the metal foils into lines.
    Type: Grant
    Filed: May 26, 2004
    Date of Patent: June 1, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Ohsumi, Kenji Terada, Kohichi Yamazaki
  • Publication number: 20100071950
    Abstract: A wiring board is comprised of a plurality of circular semiconductor element connection pads deposited in a lattice form onto a mounting portion of an insulation substrate, their upper surfaces being connected to electrodes of a semiconductor element, and a solder resist layer deposited onto the insulation substrate, which covers the side surfaces of these pads and exposes the upper surfaces of these pads. The solder resist layer has a concave part whose bottom surface corresponds to at least all the upper surfaces of these pads.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 25, 2010
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Kohichi OHSUMI
  • Patent number: 7540082
    Abstract: A printed wiring board having a through hole conductor formed on the surface of a through hole formed in a copper-clad laminate board, and on the surface of the copper-clad laminate board 1 in the vicinity of an opening of the through hole. The through hole conductor is filled with a positive photosensitive resin. A capped conductor is formed on the positive photosensitive resin and is coupled to the through hole conductor. Further, a circuit pattern is formed on the surface of the copper-clad laminate board. An insulating layer is formed on the surface of the copper-clad laminate board, capped conductor, and the circuit pattern, and formed with a via hole extending from the surface of the insulating layer to the capped conductor. A via conductor is formed inside the via hole and on the surface of the insulating layer in the vicinity of an opening of the via hole.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kohichi Ohsumi, Kaoru Kobayashi
  • Publication number: 20080302563
    Abstract: In a wiring board, insulation layers and wiring conductors are alternately laminated, and a plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged side by side on the outermost insulation layer. Each of the wiring conductors partly has a connection pad to which the electrode terminals of the semiconductor elements are connected by flip-chip bonding. In the wiring board, a solder resist layer is deposited over the outermost insulation layer and the strip-shaped wiring conductors so as to have slit-shaped openings for exposing the upper surfaces of the connection pads. The solder resist layer fills up the space between the connection pads adjacent to each other and exposed within the slit-shaped openings.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 11, 2008
    Inventor: Kohichi Ohsumi
  • Publication number: 20080257597
    Abstract: The present invention provides a method of manufacturing printed a circuit board capable of formation of via holes having a low aspect ratio and formation of fine lines, and a printed circuit board manufactured by the method. The method of manufacturing a printed circuit board 10 according to the present invention includes a step of selectively forming a plating layer 16 for lands 22a and 22b on a metal foil 14 on the printed circuit board 10, a step of adjusting the thickness of the plating layer 16, and a step of forming the metal foil 14 into lines 14a. The aspect ratio of via holes 28 formed on lands 22a and 22b can be adjusted by adjusting the thickness of the lands 22a and 22b.
    Type: Application
    Filed: September 27, 2007
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kohichi Ohsumi, Kenji Terada, Kohichi Yamazaki
  • Publication number: 20070124929
    Abstract: A printed wiring board having a through hole conductor formed on the surface of a through hole formed in a copper-clad laminate board, and on the surface of the copper-clad laminate board 1 in the vicinity of an opening of the through hole. The through hole conductor is filled with a positive photosensitive resin. A capped conductor is formed on the positive photosensitive resin and is coupled to the through hole conductor. Further, a circuit pattern is formed on the surface of the copper-clad laminate board. An insulating layer is formed on the surface of the copper-clad laminate board, capped conductor, and the circuit pattern, and formed with a via hole extending from the surface of the insulating layer to the capped conductor. A via conductor is formed inside the via hole and on the surface of the insulating layer in the vicinity of an opening of the via hole.
    Type: Application
    Filed: August 19, 2004
    Publication date: June 7, 2007
    Inventors: Kohichi Ohsumi, Kaoru Kobayashi
  • Publication number: 20040222015
    Abstract: The present invention provides a method of manufacturing printed a circuit board capable of formation of via holes having a low aspect ratio and formation of fine lines, and a printed circuit board manufactured by the method. The method of manufacturing a printed circuit board 10 according to the present invention includes a step of selectively forming a plating layer 16 for lands 22a and 22b on a metal foil 14 on the printed circuit board 10, a step of adjusting the thickness of the plating layer 16, and a step of forming the metal foil 14 into lines 14a. The aspect ratio of via holes 28 formed on lands 22a and 22b can be adjusted by adjusting the thickness of the lands 22a and 22b.
    Type: Application
    Filed: May 26, 2004
    Publication date: November 11, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kohichi Ohsumi, Kenji Terada, Kohichi Yamazaki