Patents by Inventor Kohichi Ueda

Kohichi Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Divider circuit which calculates an integral quotient of an integral divisor
    Patent number: 5485414
    Abstract: A divider circuit which calculates an integral quotient of an integral divisor and an integral dividend. A first multiplication unit calculates products of the integral divisor and all n-bit pattern values of an n-bit pattern, where n is a predetermined number and the n-bit pattern values respectively correspond to the calculated products. A calculation unit sets the integral dividend as an initial value of an operational integer, specifies a product among the products calculated by the first multiplication unit of which the subordinate n-bit value is equal to the subordinate n-bit value of the operational integer, and calculates a difference of the operational integer and the specified product. When the difference calculated by the calculation unit is not zero, an activation unit sets a new operational integer by canceling the subordinate n bits of the difference and causes the calculation unit to set the integral dividend, specify a product and calculate a difference based on the new operational integer.
    Type: Grant
    Filed: March 17, 1994
    Date of Patent: January 16, 1996
    Assignee: Fujitsu Limited
    Inventors: Mitsuyoshi Yao, Kohichi Ueda
  • Floating-point addition/subtraction system with digit position alignment between fractions of multiple sets of data
    Patent number: 5016209
    Abstract: A system of floating-point addition/subtraction for two sets of data includes a first shifting control data generating unit, a second shifting control data generating unit, a first shifting unit, and a second shifting unit. The first shifting control data generating unit generates a shifting control data based on a comparison between the lower bits of the characteristics of the two sets of data. The second shifting unit generates a shifting control data based on a comparison between the entire bits of the characteristics of the two sets of data. The digit position alignment between the fractions of the two sets of data is attained by carrying out the shifting control data generation in parallel with the shifting operation.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: May 14, 1991
    Assignee: Fujitsu Limited
    Inventors: Masayuki Ikeda, Kohichi Ueda
  • Multichip data shifting system
    Patent number: 4490809
    Abstract: In a multichip shifter, input data is applied to a plurality of rotators which rotate the input data by 2.sup.A bits. The outputs from the rotators are applied to selectors which select between the rotated outputs. The selected outputs are then shifted in shifters by from 0 to 2.sup.A -1 bits.
    Type: Grant
    Filed: August 22, 1980
    Date of Patent: December 25, 1984
    Assignee: Fujitsu Limited
    Inventors: Kohichi Ueda, Shigemi Kamimoto, Akira Miyata