Patents by Inventor Kohji Ariga

Kohji Ariga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11957014
    Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 9, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11950462
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 2, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue, Hiroharu Jinmura, Takeshi Yaneda
  • Patent number: 11908873
    Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 20, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
  • Patent number: 11889728
    Abstract: A display device includes: a resin substrate; a TFT layer; and a light-emitting element. A bending portion is provided with a first resin film formed of the same material and in the same layer as those of a first flattening film, and the first resin film fills a slit. An upper face of the first resin film is provided with a plurality of first connection wiring lines formed of a third metal film, and the plurality of first connection wiring lines extend in parallel to each other in a direction intersecting the extending direction of the bending portion. The plurality of first connection wiring lines are electrically connected to a plurality of first lead-out wiring lines, respectively in a display region side of the slit, and electrically connected to a plurality of second lead-out wiring lines, respectively in a terminal portion side of the slit.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: January 30, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Shinsuke Saida, Shoji Okazaki, Tokuo Yoshida, Hiroki Taniyama, Kohji Ariga, Hiroharu Jinmura, Akira Inoue, Yoshihiro Nakada, Yoshihiro Kohara, Koji Tanimura
  • Patent number: 11793041
    Abstract: In a TFT layer provided on a base substrate, a first metal film, a first inorganic insulating film, a second metal film, a second inorganic insulating film, a third metal film, a first flattening film, a fourth metal film, and a second flattening film are sequentially layered. In a frame region, a slit is formed in the second flattening film to surround a display region, a first conductive layer formed by the fourth metal film is provided on the first flattening film exposed from the slit, and a TFT of a drive circuit is provided on the base substrate side of the first conductive layer to overlap with the first conductive layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 17, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Kohji Ariga, Hiroki Taniyama, Shinji Ichikawa, Shinsuke Saida, Hiroharu Jinmura, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada
  • Patent number: 11659749
    Abstract: In a display region, each first power-source line and each second power-source line intersecting with the first power-source line are electrically connected together via a contact hole in a second inorganic insulating film. In addition, each source line and each second power-source line intersect with each other via the second inorganic insulating film and a first organic insulating film.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: May 23, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Hiroki Taniyama, Ryosuke Gunji, Shinji Ichikawa, Kohji Ariga, Akira Inoue, Yoshihiro Kohara, Koji Tanimura, Yoshihiro Nakada, Hiroharu Jinmura
  • Patent number: 11626449
    Abstract: In a display device, an inorganic insulating layer, a metal layer, a flattering film, a first electrode, an edge cover, a function layer, and a second electrode are formed, in that order, on a base substrate. The edge cover covers an edge of the first electrode and includes a first opening exposing the first electrode. The function layer is formed covering the first opening and an edge of the edge cover. The flattening film includes a first planar portion and a second planar portion having a film thickness smaller than that of the first planar portion, is configured to electrically connect the first electrode and the metal layer via a contact hole formed in the first planar portion, and overlaps the first opening of the edge cover at at least a portion of the second planar portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: April 11, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Kohji Ariga, Hiroki Taniyama, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11574983
    Abstract: In a display device, a second wiring line extends in a display region and includes an imaginary straight line that extends from the second wiring line in an extension direction of the second wiring line and intersects with an opening of an edge cover. The second wiring line extends along the peripheral edge of the opening without intersecting with the opening of the edge cover.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 7, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Ryosuke Gunji, Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Kohji Ariga, Hiroki Taniyama, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11508792
    Abstract: In a display region, etching stopper layers are provided between a plurality of inorganic insulating films, openings are formed in the inorganic insulating films located closer to a light-emitting element than the etching stopper layers so as to expose the upper surfaces of the etching stopper layers, and flattening films are provided in the openings such that the openings are filed with the flattening films.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 22, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinji Ichikawa, Kohji Ariga, Shinsuke Saida, Hiroki Taniyama, Hiroharu Jinmura, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Akira Inoue
  • Patent number: 11398542
    Abstract: In a step of forming a plurality of control lines composed of a first metal layer a first metal layer branch line is formed. In a step of forming a plurality of power source lines composed of a second metal layer a second metal layer connecting portion is formed that connects each power source line with the first metal layer branch line via an opening of a first insulating film. In a step of forming a plurality of data signal lines composed of a third metal layer that is formed on a second insulating film the first metal layer branch line formed in the opening of the first insulating and the second metal layer connecting portion formed in an opening of the second insulating film are etched.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: July 26, 2022
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Shinsuke Saida, Shinji Ichikawa, Hiroki Taniyama, Ryosuke Gunji, Kohji Ariga, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Publication number: 20210367027
    Abstract: In a display region, each first power-source line and each second power-source line intersecting with the first power-source line are electrically connected together via a contact hole in a second inorganic insulating film. In addition, each source line and each second power-source line intersect with each other via the second inorganic insulating film and a first organic insulating film.
    Type: Application
    Filed: May 10, 2018
    Publication date: November 25, 2021
    Inventors: Tohru OKABE, Shinsuke SAIDA, Hiroki TANIYAMA, Ryosuke GUNJI, Shinji ICHIKAWA, Kohji ARIGA, Akira INOUE, Yoshihiro KOHARA, Koji TANIMURA, Yoshihiro NAKADA, Hiroharu JINMURA
  • Publication number: 20210313412
    Abstract: A display devise includes: a resin substrate; a TFT layer; and a light-emitting element. A bending portion is provided with a first resin film formed of the same material and in the same layer as those of a first flattening film, and the first resin film fills a slit. An upper face of the first resin film is provided with a plurality of first connection wiring lines formed of a third metal film, and the plurality of first connection wiring lines extend in parallel to each other in a direction intersecting the extending direction of the bending portion. The plurality of first connection wiring lines are electrically connected to a plurality of first lead-out wiring lines, respectively in a display region side of the slit, and electrically connected to a plurality of second lead-out wiring lines, respectively in a terminal portion side of the slit.
    Type: Application
    Filed: August 28, 2018
    Publication date: October 7, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINJI ICHIKAWA, SHINSUKE SAIDA, SHOJI OKAZAKI, TOKUO YOSHIDA, HIROKI TANIYAMA, KOHJI ARIGA, HIROHARU JINMURA, AKIRA INOUE, YOSHIHIRO NAKADA, YOSHIHIRO KOHARA, KOJI TANIMURA
  • Publication number: 20210288129
    Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein insular semiconductor lines between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of waisted portions.
    Type: Application
    Filed: July 30, 2018
    Publication date: September 16, 2021
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA, RYOSUKE GUNJI, KOHJI ARIGA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, HIROHARU JINMURA, AKIRA INOUE
  • Publication number: 20210225881
    Abstract: An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires.
    Type: Application
    Filed: August 23, 2018
    Publication date: July 22, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINJI ICHIKAWA, SHINSUKE SAIDA, SHOJI OKAZAKI, TOKUO YOSHIDA, HIROKI TANIYAMA, KOHJI ARIGA, HIROHARU JINMURA, AKIRA INOUE, YOSHIHIRO NAKADA, YOSHIHIRO KOHARA, KOJI TANIMURA
  • Publication number: 20210210583
    Abstract: In a TFT layer provided on a base substrate, a first metal film, a first inorganic insulating film, a second metal film, a second inorganic insulating film, a third metal film, a first flattening film, a fourth metal film, and a second flattening film are sequentially layered. In a frame region, a slit is formed in the second flattening film to surround a display region, a first conductive layer formed by the fourth metal film is provided on the first flattening film exposed from the slit, and a TFT of a drive circuit is provided on the base substrate side of the first conductive layer to overlap with the first conductive layer.
    Type: Application
    Filed: May 22, 2018
    Publication date: July 8, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, KOHJI ARIGA, HIROKI TANIYAMA, SHINJI ICHIKAWA, SHINSUKE SAIDA, HIROHARU JINMURA, AKIRA INOUE, YOSHIHIRO KOHARA, KOJI TANIMURA, YOSHIHIRO NAKADA
  • Publication number: 20210098559
    Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.
    Type: Application
    Filed: March 30, 2018
    Publication date: April 1, 2021
    Inventors: HIROKI TANIYAMA, RYOSUKE GUNJI, SHINSUKE SAIDA, SHINJI ICHIKAWA, TOHRU OKABE, KOHJI ARIGA, AKIRA INOUE, YOSHIHIRO KOHARA, KOJI TANIMURA, YOSHIHIRO NAKADA, HIROHARU JINMURA
  • Publication number: 20210057512
    Abstract: In a display device, a second wiring line extends in a display region and includes an imaginary straight line that extends from the second wiring line in an extension direction of the second wiring line and intersects with an opening of an edge cover. The second wiring line extends along the peripheral edge of the opening without intersecting with the opening of the edge cover.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 25, 2021
    Inventors: RYOSUKE GUNJI, TOHRU OKABE, SHINSUKE SAIDA, SHINJI ICHIKAWA, KOHJI ARIGA, HIROKI TANIYAMA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, HIROHARU JINMURA, AKIRA INOUE
  • Publication number: 20210050395
    Abstract: In a display region, etching stopper layers are provided between a plurality of inorganic insulating films, openings are formed in the inorganic insulating films located closer to a light-emitting element than the etching stopper layers so as to expose the upper surfaces of the etching stopper layers, and flattening films are provided in the openings such that the openings are filed with the flattening films.
    Type: Application
    Filed: March 28, 2018
    Publication date: February 18, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINJI ICHIKAWA, KOHJI ARIGA, SHINSUKE SAIDA, HIROKI TANIYAMA, HIROHARU JINMURA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, AKIRA INOUE
  • Publication number: 20210036093
    Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.
    Type: Application
    Filed: March 30, 2018
    Publication date: February 4, 2021
    Inventors: TOHRU OKABE, SHINSUKE SAIDA, SHINJI ICHIKAWA, HIROKI TANIYAMA, RYOSUKE GUNJI, KOHJI ARIGA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, AKIRA INOUE, HIROHARU JINMURA, TAKESHI YANEDA
  • Publication number: 20210020689
    Abstract: In a display device, an inorganic insulating layer, a metal layer, a flattering film, a first electrode, an edge cover, a function layer, and a second electrode are formed, in that order, on a base substrate. The edge cover covers an edge of the first electrode and includes a first opening exposing the first electrode. The function layer is formed covering the first opening and an edge of the edge cover. The flattening film includes a first planar portion and a second planar portion having a film thickness smaller than that of the first planar portion, is configured to electrically connect the first electrode and the metal layer via a contact hole formed in the first planar portion, and overlaps the first opening of the edge cover at at least a portion of the second planar portion.
    Type: Application
    Filed: March 22, 2018
    Publication date: January 21, 2021
    Inventors: TOHRU OKABE, RYOSUKE GUNJI, SHINSUKE SAIDA, SHINJI ICHIKAWA, KOHJI ARIGA, HIROKI TANIYAMA, YOSHIHIRO NAKADA, KOJI TANIMURA, YOSHIHIRO KOHARA, HIROHARU JINMURA, AKIRA INOUE