Abstract: Frame wiring lines are provided in a frame region, a flattening film in which a frame-shaped slit is formed in the frame region is provided in the display region and the frame region, a plurality of first electrodes constituting light-emitting elements are provided on the flattening film, and conductive layer made of the same material and formed in the same layer as those of each of the plurality of first electrodes are provided covering at least end faces of the frame wiring lines exposed from the slit.

Abstract: A display device includes: a plurality of control lines; a plurality of power supply lines; a plurality of data signal lines; an oxide semiconductor layer; a first metal layer; a gate insulation film; a first inorganic insulation film; a second metal layer; a second inorganic insulation film; and a third metal layer. The oxide semiconductor layer, in a plan view, contains therein semiconductor lines formed as isolated regions between a plurality of drivers and a display area. The semiconductor lines cross the plurality of control lines and the plurality of power supply lines, are in contact with the plurality of control lines via an opening in a gate insulation film, are in contact with the plurality of power supply lines via an opening in the first inorganic insulation film, and have a plurality of narrowed portions, such that thicker and thinner regions exist along the same line.

Abstract: A first conductive layer in the same layer as that of a first electrode is coupled to a third conductive layer and a second electrode in the same layer as that of a third metal layer through a slit formed in a flattening film of a non-display area. Second conductive layers in the same layer as that of a second metal layer are provided to overlap with the slit.

Abstract: A divider constituted by connecting in series a plurality of arithmetic units in such a manner as to correspond to the number of bits of first data, said divider comprising: a divisor data input unit for inputting a complement of 2 of divisor data in division as said first data signal lines for sending dividend data and said addition result data calculated by said arithmetic unit on the basis of said dividend data and selected by said selector of said arithmetic unit or said carry output data from said arithmetic unit of the most significant bit among said arithmetic units for effecting the arithmetic operation using said second data, as said second data; and an AND circuit for calculating a logical product between a logical product for each bit of said divisor data and said carry output data sent from said signal line, and supplying said logical product as said select signal to said selector.

Abstract: A converter is provided having a layout which can be easily designed and which requires a small chip area. Four MOS transistors having the same layout are disposed on the same substrate, and a polycrystalline silicon layer extends under the MOS transistors in the substrate. A predetermined voltage is applied to the polycrystalline silicon layer. This applied voltage continuously controls threshold voltages of the MOS transistors. An analog signal is input to gate terminals of the MOS transistors and is digitized in accordance with on and off states of the MOS transistors.