Abstract: A divider constituted by connecting in series a plurality of arithmetic units in such a manner as to correspond to the number of bits of first data, said divider comprising: a divisor data input unit for inputting a complement of 2 of divisor data in division as said first data signal lines for sending dividend data and said addition result data calculated by said arithmetic unit on the basis of said dividend data and selected by said selector of said arithmetic unit or said carry output data from said arithmetic unit of the most significant bit among said arithmetic units for effecting the arithmetic operation using said second data, as said second data; and an AND circuit for calculating a logical product between a logical product for each bit of said divisor data and said carry output data sent from said signal line, and supplying said logical product as said select signal to said selector.

Abstract: A converter is provided having a layout which can be easily designed and which requires a small chip area. Four MOS transistors having the same layout are disposed on the same substrate, and a polycrystalline silicon layer extends under the MOS transistors in the substrate. A predetermined voltage is applied to the polycrystalline silicon layer. This applied voltage continuously controls threshold voltages of the MOS transistors. An analog signal is input to gate terminals of the MOS transistors and is digitized in accordance with on and off states of the MOS transistors.