Abstract: In a scan flip-flop circuit, a first master latch circuit receives usual mode data at a usual data input terminal in synchronization with a first clock signal. A second master latch circuit receives scan-in data at a scan-in data input terminal in synchronization with first and second scan clock signals. A slave latch circuit receives an output signal of the first master latch circuit in synchronization with said first clock signal and the second scan clock signal. The slave latch circuit is constructed by a control circuit for controlling transfer of the usual mode data to the output terminal in synchronization with the second scan clock signal.

Abstract: A slave latch circuit has a gate for being supplied with a signal which is an inversion of a signal outputted from a first output terminal and a control'signal, generating a signal based on the supplied signals, and outputting the generated signal from a second output terminal. The gate controls the output signal outputted from the second output terminal. The gate may comprise a NAND gate for being supplied with a ground potential as the control signal in a normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a power supply potential. Alternatively, the gate may comprise a NOR gate for being supplied with the power supply potential as the control signal in the normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a ground potential.

Abstract: In a scan flip-flop circuit, a first master latch circuit receives usual mode data at a usual data input terminal in synchronization with a first clock signal. A second master latch circuit receives scan-in data at a scan-in data input terminal in synchronization with first and second scan clock signals. A slave latch circuit receives an output signal of the first master latch circuit in synchronization with said first clock signal and the second scan clock signal. The slave latch circuit is constructed by a control circuit for controlling transfer of the usual mode data to the output terminal in synchronization with the second scan clock signal.

Abstract: A slave latch circuit has a gate for being supplied with a signal which is an inversion of a signal outputted from a first output terminal and a control signal, generating a signal based on the supplied signals, and outputting the generated signal from a second output terminal. The gate controls the output signal outputted from the second output terminal. The gate may comprise a NAND gate for being supplied with a ground potential as the control signal in a normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a power supply potential. Alternatively, the gate may comprise a NOR gate for being supplied with the power supply potential as the control signal in the normal mode of operation for thereby fixing the output signal outputted from the second output terminal to a ground potential.

Abstract: A scan flip-flop circuit includes first and second master latches, a slave latch, and first, second, and third switches. The first master latch latches a data input signal and outputs it to the first output terminal in normal operation. The second master latch latches a scan input signal and outputs it to the second output terminal in a scan test. The slave latch latches an output from the first master latch that is input to a first input terminal, thereby outputting it to a third output terminal in normal operation, and latches an output from the second master latch that is input to a second input terminal, thereby outputting it to the third output terminal in a scan test. The first switch disconnects the first output terminal of the first master latch from the first input terminal of the slave latch in a scan test. The second switch disconnects the first output terminal of the second master latch from the second input terminal of the slave latch in normal operation.

Abstract: A race-free shift register device having a plurality of series-connected flip-flop circuits and latch circuits. By a delay circuit, the timing of a clock signal input to each individual flip-flop circuit is delayed with respect to the clock signal input to the associated latch circuit, so that the operating timing of the latch circuit is not delayed with respect to the operating timing of the flip-flop circuit, even if a skew happens to occur in the clock signal. The latch circuit therefore surely holds bit data output by the flip-flop circuit, so the bit data to be input to a preceding flip-flop circuit is prevented from being prematurely provided to a succeeding flip-flop circuit, thereby ensuring prevention of a race condition.