Patents by Inventor Kohji Matsunaga

Kohji Matsunaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200410141
    Abstract: An information protection device includes: a random-contact mechanical Hall element provided with a conductive plate that has a prescribed conductive pattern, and a contact plate that is stacked on the conductive plate and that has, in an interior thereof, a connection potion partially contacting the conductive pattern; a communication line having multiple signal wires that are respectively connected to the connection portion in the random-contact mechanical Hall element; and a control unit configured to, through the communication line, monitor connection information between the connection portion and the conductive pattern in the random-contact mechanical Hall element, and determine, based on the connection information, whether or not iniquity has occurred in accordance with whether or not a connection state between the conductive pattern and the connection portion has changed from an initial setting.
    Type: Application
    Filed: February 21, 2019
    Publication date: December 31, 2020
    Applicant: NEC Platforms, Ltd.,
    Inventors: Kohji MATSUNAGA, Kunihiko ENDOH
  • Patent number: 7863648
    Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ?Lol/Lg?1 holds.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: January 4, 2011
    Assignee: NEC Corporation
    Inventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
  • Patent number: 7800131
    Abstract: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: September 21, 2010
    Assignee: NEC Corporation
    Inventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
  • Publication number: 20090230430
    Abstract: A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.
    Type: Application
    Filed: June 12, 2006
    Publication date: September 17, 2009
    Applicant: NEC CORPRORATION
    Inventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Kazuki Ota, Aklo Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
  • Publication number: 20090230429
    Abstract: A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0?Lol/Lg?1 holds.
    Type: Application
    Filed: June 12, 2006
    Publication date: September 17, 2009
    Applicant: NEC CORPORATION
    Inventors: Hironobu Miyamoto, Yuji Ando, Yasuhiro Okamoto, Tasuo Nakayama, Takashi Inoue, Kazuki Ota, Akio Wakejima, Kensuke Kasahara, Yasuhiro Murase, Kohji Matsunaga, Katsumi Yamanoguchi, Hidenori Shimawaki
  • Patent number: 7518468
    Abstract: A power distribution and combination circuit for distributing a signal input from a first port to a second and third ports and combining signals input from the second and the third port so as to be outputted to the first port. A transmission line of the power distribution and combination circuit has a first end connected to a power (the first port) and a second end connected to the second and third ports for distributing and combining the input signals. A second transmission line has a first end connected directly to the second end of the transmission line and a second end connected to the third port so as to be unified with the transmission line.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: April 14, 2009
    Assignee: NEC Corporation
    Inventor: Kohji Matsunaga
  • Publication number: 20060279378
    Abstract: There is provided a power distribution and combination circuit for distributing a signal input from a first port to a second and third ports and combining signals input from the second and thee third port so as to be outputted to the first port. A transmission line (1) of the power distribution and combination circuit (10) has one end (1) connected to a power (P1) and the other end (2) connected to ports (P2, P3) for distributing and combining the input signals. A transmission line (12) has one end connected directly to the end (2) of the transmission line (11) and the other end (3) connected to the port (P3) so as to be unified with the transmission line (11). With this configuration, it is possible to reduce the size and accordingly, it is possible to reduce the cost.
    Type: Application
    Filed: May 28, 2004
    Publication date: December 14, 2006
    Inventor: Kohji Matsunaga
  • Patent number: 6765241
    Abstract: A group III nitride semiconductor device of field effect transistor type having improved productivity, reduced parasitic capacitances adapted for excellent device performance in high-speed operation as well as good heat diffusion characteristics. The device includes an epitaxial growth layer of a group III nitride semiconductor with a buffer layer laid under it, formed on an A plane (an (11-20) plane) of a sapphire. Thereon a gate electrode, a source electrode, a drain electrode, and pad electrodes are formed, and a ground conductor layer is formed on the back face of the sapphire substrate. A thickness of said sapphire substrate tsub satisfies the following Equation (1).
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: July 20, 2004
    Assignee: NEC Corporation
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Publication number: 20030151064
    Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, the heat diffusion characteristic and the device performance in high-speed operation, and, therefor, in a group III nitride semiconductor device of the present invention, an epitaxial growth layer 13 of a group III nitride semiconductor with a buffer layer 12 laid under it is formed on a sapphire substrate 11 in which an A plane (an (11-20) plane) is set to be the principal plane, and thereon a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed, wherein a thickness of the single crystalline sapphire substrate is specifically set to be 100 &mgr;m or less.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 14, 2003
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Publication number: 20020171096
    Abstract: In a field effect transistor, there are provided a gate electrode on a Schottky layer over an InP channel layer over the substrate, and a field control electrode extending over an insulating layer and separated from the Schottky layer and being positioned between the gate electrode and the drain electrode for controlling an expansion of a space charge region in the channel layer.
    Type: Application
    Filed: May 17, 2002
    Publication date: November 21, 2002
    Applicant: NEC CORPORATION
    Inventors: Akio Wakejima, Kazuki Ota, Kohji Matsunaga, Walter Contrata, Masaaki Kuzuhara
  • Patent number: 6441391
    Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: August 27, 2002
    Assignee: NEC Corporation
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, Kohji Matsunaga, Masaaki Kuzuhara
  • Publication number: 20020047113
    Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, heat radiation characteristic and performance in the element high speed operation; upon a sapphire substrate in which an A plane (an (11-20) plane) is set to be the basal plane, an epitaxial growth layer of a group III nitride semiconductor is formed and, thereon, a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed; these electrodes are disposed in such a way that a direction along which they are laid makes an angle within 20° with respect to a C axis of sapphire.
    Type: Application
    Filed: August 29, 2001
    Publication date: April 25, 2002
    Applicant: NEC CORPORATION
    Inventors: Yasuo Ohno, Nobuyuki Hayama, Kensuke Kasahara, Tatsuo Nakayama, Hironobu Miyamoto, Yuji Takahashi, Yuji Ando, kohji Matsunaga, Masaaki Kuzuhara
  • Patent number: 6166604
    Abstract: A semiconductor amplifier with a compensated passing gain characteristic and passing phase characteristic is disclosed. Connected to an input to a non-linear amplifying element is a characteristic improving circuit comprising a passive circuit including a capacitor, a resistor, and an inductor, and an FET connected to the passive circuit and having its source and a drain both grounded. In the characteristic improving circuit, with an increase in the input level, a gate capacitance of the FET is increased to enhance the passing gain and reduce the passing phase. Such characteristics of the characteristic improving circuit compensate for the characteristics of the FET to improve a phase characteristic and a distortion characteristic of the non-linear amplifying element at an output level.
    Type: Grant
    Filed: June 15, 1999
    Date of Patent: December 26, 2000
    Assignee: NEC Corporation
    Inventor: Kohji Matsunaga
  • Patent number: 5084131
    Abstract: A fabrication method for thin film electroluminescent panels including steps of forming a composite film by depositing Ni film on Al film for forming back electrodes and lead-out electrodes, forming a resist pattern on the composite film and etching the composite film into a predetermined pattern so as to form back electrodes and lead-out electrodes using an etchant containing phosphoric acid of 3.5 to 13.0 mol/l, sulphuric acid of 0.1 to 9.0 mol/l, nitric acid of 0.1 to 8.0 mol/l and acetic acid of 0.0 to 8.0 mol/l.
    Type: Grant
    Filed: January 11, 1991
    Date of Patent: January 28, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mayumi Inoue, Kohji Matsunaga, Tomizoh Matsuoka