Abstract: To generate a dot clock for a liquid crystal display device from a horizontal sync signal with reduced skew, a phase locked loop (PLL) is divided into three functional parts. The first part generates a particular frequency by supplying voltage from a latch type DAC (digital/analog converter) to a VCO (voltage controller oscillator). A horizontal sync signal is estimated from the dot clock signal that is finally generated and the output value of the DAC is increased or decreased in accordance with the difference between this estimated horizontal sync signal and the actual horizontal sync signal. This increase or decrease correction is made at, for example, the vertical sync timing. The second part achieves synchronization. A signal corresponding to the phase error between the actual horizontal sync signal and the dot clock signal is added to the signal from the DAC to control the phase of the dot clock.