Abstract: Conventionally, when executing a plurality of programs while being synchronized by a plurality of debuggers, an interface has been required for performing a particular coordination between the debuggers. In the present invention, programs are synchronously executed without coordination between the debuggers by performing a control method including a step for maintaining a program execution state in the debuggers to be different from an actual program execution state, so that the program execution is retained, if necessary, in response to a program execution request from a debugger.

Abstract: Conventionally, when executing a plurality of programs while being synchronized by a plurality of debuggers, an interface has been required for performing a particular coordination between the debuggers. In the present invention, programs are synchronously executed without coordination between the debuggers by performing a control method including a step for maintaining a program execution state in the debuggers to be different from an actual program execution state, so that the program execution is retained, if necessary, in response to a program execution request from a debugger.

Abstract: In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.

Abstract: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided.

Abstract: The debug device of the present invention is a debug device which stops execution of a program based on one of a conditional break for stopping the program regardless of the condition of a predicated instruction and an unconditional break for stopping the program only when the condition of the predicated instruction is true. The debug device includes: a receiving unit which receives a breakpoint according to an operation by a user; a determination unit which determines the received break point as the unconditional break or the conditional break; and a stop unit operable to stop the program based on the unconditional break or the conditional break determined by the determination unit.

Abstract: A simulation apparatus for simulating a pipeline processor including a pipeline simulation unit and an instruction simulation unit. The simulation apparatus includes a pipeline simulation unit is operable to simulate a group of instructions comprising a plurality of instructions to be executed simultaneously. The instruction simulation unit is operable to simulate a sequential execution, of the group of instructions on an instruction-by-instruction basis, based on the simulation result performed by the pipeline simulation unit. The instruction simulation unit generates the simulation result by undoing the simulation where an instruction included in the group of instructions that has just been simulated by the pipeline simulation unit.

Abstract: A processor according to the present invention is capable of executing instructions in parallel, the processor further executing a string of instructions consisting of a plurality of instructions allocated at continuous addresses as an execution unit, comprising an instruction analyzer, an instruction executor and an instruction canceling unit. The instruction analyzer comprising debug instruction detectors for detecting a debug instruction which generates debug interruption, the instruction detectors of the same number as the instructions executable in parallel by the processor is provided.

Abstract: In executing debugging of an executable program in which a breakpoint is set at a conditional instruction using a software break technique, judgment of whether or not to stop the debugging is made, without use of a debugging device, in accordance with whether an execution condition expression of the conditional instruction is true or false. A processor capable of decoding and executing a program that includes conditional instructions executes debugging of the program. When a decoded instruction is a conditional break instruction (S201: YES, S202: YES), the processor identifies the type of the execution condition of the conditional break instruction (step S203), and refers to a status register to check a status flag of the execution condition (S204). If the execution condition is satisfied (S205: YES), the processor executes interrupt processing to suspend debugging (S206), and if the execution condition is not satisfied (S205: NO), the processor continues debugging.

Abstract: A debugging device according to the present invention comprises a host communication section for transmitting and receiving data to and from a host computer, a target communication section for transmitting and receiving data to and from a target CPU as an object to be debugged, an external storage medium for storing a unique discrimination code for identifying the storage medium and an encrypted license information, and a control section for decoding the license information using a predetermined secret key and judging whether or not the license information is valid using the discrimination code.

Abstract: The system performance evaluation method of the present invention confirms the existence of the occurrence of a memory access penalty for each cycle (S101) and executes a CPU model only when a memory access penalty has not occurred (S202).

Abstract: Provided is a cache memory system which, in a system having a plurality of masters, effectively utilizes a bus band. The cache memory system comprises: a cache memory; a bus load judging device for performing judgment of a state of a bus that is connected to a recording device in which cache-target data of the cache memory is stored; and a replace-way controller for controlling a replacing form of the cache memory according to a result of judgment performed by the bus load judging device.

Abstract: In the case where a break instruction is a predicated instruction whose execution condition is not satisfied in a program debug apparatus, the target program is executed again up to the predicated instruction, that is to be executed next, whose execution condition is satisfied or the non-predicated instruction that is to be executed next.

Abstract: The simulation apparatus of the present invention is a simulation apparatus that is intended for a pipeline processor that executes a plurality of instructions simultaneously, and it comprises a pipeline simulation unit operable to simulate a group of instructions comprising a plurality of instructions to be executed simultaneously and an instruction simulation unit operable to generate the simulation result of the group of instructions on an instruction-by-instruction basis based on the simulation result performed by the pipeline simulation unit, and the instruction simulation unit generates the simulation result by undoing the simulation where an instruction included in the group of instructions that has just been simulated by the pipeline simulation unit.