Patents by Inventor Kohsuke Ikeda

Kohsuke Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory cell and semiconductor memory device
    Patent number: 6373745
    Abstract: The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors 10 and 12 and one inverter circuit 14. The source terminal of PMOS transistor 10 is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source tenninal of NMOS transistor 12 is connected to a supply voltage terminal that provides low-level reference potential VSS (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit 14. The input terminal of inverter circuit 14 is connected to data storage node (Na).
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: April 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Yoritaka Saito, Hiroshi Ikeda, Takumi Nasu, Kohsuke Ikeda, Yoshinobu Matsumoto, Satoshi Nakayama, Yasuhito Ichimura
  • Semiconductor memory cell and semiconductor memory device
    Publication number: 20010033511
    Abstract: The objective of this invention is to reduce the layout area while guaranteeing data retention stability in a static type semiconductor memory cell. This SRAM cell is constituted with two MOS transistors 10 and 12 and one inverter circuit 14. The source terminal of PMOS transistor 10 is connected to bit line (BL), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to word line (WL). The source terminal of NMOS transistor 12 is connected to a supply voltage terminal that provides low-level reference potential VSS (for example, zero volts), the drain terminal is connected to data storage node (Na), and the gate terminal is connected to the output terminal o inverter circuit 14. The input terminal of inverter circuit 14 is connected to data storage node (Na).
    Type: Application
    Filed: March 21, 2001
    Publication date: October 25, 2001
    Inventors: Yoritaka Saito, Hiroshi Ikeda, Takumi Nasu, Kohsuke Ikeda, Yoshinobu Matsumoto, Satoshi Nakayama, Yasuhito Ichimura
  • Dynamic memory
    Patent number: 6115282
    Abstract: The objective is to provide a type of dynamic memory which does not adversely affect the data, even when noise is superimposed on the RAS signal.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: September 5, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Koichi Abe, Takashi Inui, Kohsuke Ikeda, Toshiyuki Ishiuchi