Patents by Inventor Koichi Ashiga

Koichi Ashiga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8634170
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: January 21, 2014
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20120113552
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: January 19, 2012
    Publication date: May 10, 2012
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 8139327
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: March 20, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20110090605
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: December 23, 2010
    Publication date: April 21, 2011
    Inventors: Takayasu ITO, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7881026
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 1, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20100045368
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7630178
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: December 8, 2009
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20080285185
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: July 25, 2008
    Publication date: November 20, 2008
    Inventors: TAKAYASU ITO, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7417838
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 26, 2008
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20070109699
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: December 29, 2006
    Publication date: May 17, 2007
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7177123
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: February 13, 2007
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20040085690
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Applicants: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 6683767
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: January 27, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20010054760
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 27, 2001
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga