Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories.

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced.

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced.

Abstract: There is provided a semiconductor device testing apparatus capable of greatly decreasing an interrupted time of a testing even if a board on which a test pattern supply path and/or a strobe pulse supply path is provided is replaced. A signal propagation delay time of the test pattern supply path through which a test pattern signal is supplied to a semiconductor device under test and a signal propagation delay time of the strobe pulse supply path through which a strobe pulse is supplied to a signal read circuit reading therein a logical value of a response signal outputted from the semiconductor device under test are measured respectively, and differences between the measured respective values and predetermined corresponding delay times are found respectively. The obtained time differences are stored as delay correcting data in a non-volatile memory or corresponding non-volatile memories.

Abstract: A wave formatter circuit for generating a test signal of predetermined waveform in a repetition rate determined by a pattern cycle of a semiconductor test system includes a timing generator for generating a first clock signal and a second clock signal, a waveform shaper which receives the first and second clock signals for generating a set signal and a reset signal, a flip-flop which generates a test signal of predetermined waveform at the timing determined by the set signal and the reset signal, a pattern generator for generating a test pattern data at the rate of the pattern cycle, a data selector which selects first pattern data and second pattern data from the pattern generator to be supplied to the waveform shaper, an inhibit circuit which receives the first and second pattern data from the data selector and provides an inhibit signal to the waveform shaper to prohibit either one of the first and second clock signals in the same pattern cycle passing through the waveform shaper, where the set signal and