Abstract: An object is to provide a stable delta-sigma modulator having good microlevel signal reproducibility and capable of outputting a 1-bit PDM signal with a low oversampling ratio of about 64 times at a high duty ratio of 90% or more. The delta-sigma modulator has a higher-order loop filter; a first 1-bit quantizer for making a decision as to the output of the higher-order loop filter; a first feedback component for feeding the first output signal back to the input stage of the higher-order loop filter; a second 1.5-bit quantizer for making a decision as to the output absolute value of an internal stage to be monitored; a second dynamic feedback component for feeding a second output signal back to the input stage of the higher-order loop filter; and an operational unit for producing a 1-bit PDM signal Y by performing operation on the first output signal and second output signal.

Abstract: A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

Abstract: An object is to provide a stable delta-sigma modulator having good microlevel signal reproducibility and capable of outputting a 1-bit PDM signal with a low oversampling ratio of about 64 times at a high duty ratio of 90% or more. The delta-sigma modulator has a higher-order loop filter; a first 1-bit quantizer for making a decision as to the output of the higher-order loop filter; a first feedback component for feeding the first output signal back to the input stage of the higher-order loop filter; a second 1.5-bit quantizer for making a decision as to the output absolute value of an internal stage to be monitored; a second dynamic feedback component for feeding a second output signal back to the input stage of the higher-order loop filter; and an operational unit for producing a 1-bit PDM signal Y by performing operation on the first output signal and second output signal.

Abstract: A hybrid delta sigma ADC architecture and method is disclosed to implement a high-resolution delta-sigma modulator with a single-bit output. The system contains a low-order multi-bit analog noise-shaping loop, followed by a high-order single-bit digital modulator. The combination simplifies the analog modulator, and allows the use of most of the full-scale input range.

Abstract: To provide a fully differential sampling circuit which reduces a sampling error to suppress the occurrence of a second harmonic component. The sampling error is resulted from voltage dependence of a capacitance of the capacitor formed on a semiconductor substrate. The present invention includes a first sampling capacitor 27, a second sampling capacitor 28, four switches 31, 32, 33′, and 34 for charging and discharging the first sampling capacitor 27, four switches 41, 42, 43′, and 44 for charging and discharging the second sampling capacitor 28, and a fully differential operational amplifier 20 including a first integral capacitor 25 and a second sampling capacitor 26. An upper layer electrode 28b and a lower layer electrode 28a of the second sampling capacitor 28 are opposite to the first sampling capacitor 27 in connecting direction (state).

Abstract: To provide a fully differential sampling circuit which reduces a sampling error to suppress the occurrence of a second harmonic component. The sampling error is resulted from voltage dependence of a capacitance of the capacitor formed on a semiconductor substrate.