Abstract: Two up-counters and two down-counters having a time difference corresponding to a dead time are provided to realize an up-down symmetric count, such that the up-counters and the down-counters are made to count the lower limit and the upper limit (a 1/2 period+the dead time), the up-counter for counting a relatively large value and the down-counter for counting a relatively large value are made to contact at the upper limit, the up-counter for counting a relatively small value and the down-counter for counting a relatively small value are made to intersect at a count value corresponding to the 1/2 period, the up-counter for counting the relatively large value and the down-counter for counting the relatively large value are made to intersect at the count value corresponding to the dead time, and the up-counter for counting the relatively small value and the down-counter for counting the relatively small value are made to contact at the lower limit.

Abstract: A semiconductor integrated circuit comprising a clock pulse generator, peripheral function blocks and bus master modules. The peripheral function blocks are commonly supplied with a first system clock signal of a constant frequency generated on the basis of the output from the clock pulse generator. The bus master modules are fed with a second system clock signal generated on the basis of the pulse generator output. The frequency of the second system clock signal is variable and lower than that of the first system clock signal. The function blocks supplied with the first system clock signal are connected to a data bus separate from the one connected to the function blocks fed with the second system clock signal.