Abstract: There is provided a portable electronic device limiting an allowable operating range thereof for security reason and a security system using the portable electronic device. A security system 10 includes a mobile-phone 100 and an item 101. The mobile-phone 100 has functions of a registering unit 501, a judging unit 503 and an operating range determining unit 504, etc. The registering unit 501 registers item information to specify the item in advance. The judging unit 503 judges, based on the presence or absence of a signal from the item, whether an item specified by the registered item information can communicate with the mobile-phone or not when an event is generated in the mobile-phone.

Abstract: An unfair contents appropriation detection system capable of efficiently detecting the contents intentionally changed for the worse with ill will. If a contents browser terminal 130 obtains the contents appropriated by a contents appropriator terminal 120, an unfair contents appropriation detection program is incorporated into the above contents appropriated by the contents appropriator terminal. This program transmits alarm information AL to a watcher terminal 140 when a content browser terminal obtains the unfairly appropriated contents from the unfair contents appropriator terminal 120. Furthermore, in this unfairly appropriated contents, there is embedded a digital water mark for obtaining the changed area information of the contents. The watcher terminal obtains the contents from the contents appropriator terminal based on the alarm information AL and executes verification of the digital water mark with regard to the contents as obtained.

Abstract: A testing system is provided with a pseudo random number generating circuit which generates a pseudo random number on the basis of a 125 MHz clock output from a 5-multiply circuit inside a clock recovery circuit, and an expected value generating/comparator circuit which collates a 125 Mbps recovered data output from the clock recovery circuit with an expected value data each 5 bits, and outputs the collation result as a 1-bit test output. The clock recovery circuit and the testing system are provided on the same LSI and are operated at a 125 MHz high frequency clock. However, the clock recovery circuit outputs a test output as recognized as a 25 MHz low speed data in the outside of LSI to the external elements.

Abstract: With a first-transition detecting circuit for receiving a synchronism detection signal indicating the state where synchronism of a digital signal has been established and outputting a pulse, a flip-flop for receiving this pulse and outputting a flag signal of “H” level, and logic gates, when a TMCC decoding complete signal indicating completion of a TMC signal is generated the TMCC signal inputted into a buffer anew is written in a register, and this TMCC signal is used for decoding a data stream. Then, in the state where synchronism of a digital signal has been established, updating of a TMCC signal is executed in response to output of a signal from a comparing circuit indicating inconsistency between updating instruction information newly inputted and updating instruction information already stored.

Abstract: There is provided an unfair contents appropriation detection system capable of efficiently detecting the contents intentionally changed for the worse with ill will.

Abstract: Flour blends which contain waxy wheat flour and which are suitable for the preparation of deep fried foods, steamed Chinese manju, dough sheets, okonomi-yaki, and takoyaki are described. These flour blends make it possible to obtain foods which have excellent texture and flavor when consumed immediately after preparation or after being heated or thawed.

Abstract: A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.

Abstract: Flour blends are described containing waxy wheat flour and are suitable for the preparation of breads, cakes, or noodles. These flour blends make it possible to obtain foods which do not show degraded texture after prolonged storage, and which particularly provide an excellent texture when consumed after being frozen and thawed.

Abstract: A digital PLL circuit recovers a clock signal from an analog baseband signal. The PLL circuit has a phase comparator. The phase comparator provides a loop filter with a control value for a period of the recovered clock signal after a determination is made. If the determination is that the baseband signal has crossed a transition level, the control value corresponds to a time difference between a sampling point and a transition-level crossing point of the baseband signal. If the determination is that the baseband signal has not crossed the transition level, the control value is 0. The PLL circuit shortens a lockup time and provides stable operation even if the baseband signal involves an offset.

Abstract: An arithmetic operation unit for operating according to pipeline control and an instruction decoder for controlling the arithmetic operation unit by decoding an instruction, including a state retaining unit for retaining a state of the operation of the arithmetic operation unit, wherein the instruction decoder controls the execution of the arithmetic operation unit according to the information stored by the state retaining unit. A state is set when the decoder issues a signal for starting the arithmetic operation unit and the state is cleared when the decoder issues a signal for stopping the operation of the arithmetic operation unit. The arithmetic operation unit further comprises a unit for obtaining a maximum and a minimum value with a simple construction. A multiplier of the arithmetic operation unit comprises a unit for performing an addition of an exponential part of a multiplier and that of a multiplicand with a simple construction.

Abstract: A replacement control circuit 30, having a synchronization pattern monitoring circuit 31, an acquisition circuit 32, a tracking circuit 33, an RS flip-flop 34 and an AND gate 35, judges whether receive data D3 is in synchronization or not, counts a clock CLK corresponding to a byte of the receive data D3, and while the receive data D3 is judged to be in synchronization, generates a replacement control signal S5 that becomes active at a synchronization pattern location of each packet. When the replacement control signal S5 is active, a selection circuit 43 selects synchronization pattern P1 generated by a synchronization pattern generation circuit 42. When the replacement control signal S5 is inactive, the selection circuit 43 selects the receive data D3. The output of the selection circuit 43 is corrected by a byte error correction circuit in units of packets.

Abstract: A processor comprises a command storage unit for storing a plurality of commands and data received from outside the processor, a command interpreter for interpreting commands and data stored in the command storage unit, an address designator for designating a particular execution address of the storage unit according to a command interpreted by the command interpreter or to an operation start command, and an update selector for selecting whether or not to update the value of an execution address designated by the address designator according to a command interpreted by the command interpreter.

Abstract: A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without intervention of the master processor. When the master processor activates the slave processor, the slave processor outputs a busy signal immediately (at most one cycle later). The master processor reads the value of a busy register representing a busy/ready status of the slave processor in a slave access cycle at highest speed (in two cycles at most). Regardless of whether the master processor and the slave processor was designed as series products or general purpose products, they can be effectively connected.

Abstract: A data processing system includes a single-precision operation unit, a double-precision operation unit, a single-precision data to double-precision data conversion unit, and a double-precision data to single-precision data conversion unit. When two single-precision operations are simultaneously carried out, the single-precision operation unit performs a single-precision operation upon a group of single-precision data, and the double-precision operation unit with the single-precision data to double-precision data conversion unit and the double-precision data to single-precision data conversion unit perform a single-precision operation upon the other group of single-precision data. When a double-precision operation is carried out, the double-precision operation unit performs a double-precision operation upon a group of double-precision data.

Abstract: A numeric representation converting apparatus comprises a weight determining circuit, a decimal alignment circuit, a converting circuit, and a selecting circuit. The weight determining circuit determines the weight of a mantissa part of an input floating-point number, based on the value of an exponent part of that number. The decimal alignment circuit shifts digits of the value of the mantissa based on the determined weight of the mantissa. The converting circuit converts the value of the integer part of the value obtained by the decimal alignment circuit to a representation of a negative number, and truncates the value of the negative number either in the direction of the more negative number or the less negative number. Finally, the selecting circuit outputs either the integer part of the value obtained by the decimal alignment circuit or the value obtained by the converting circuit.

Abstract: An information protective device protects stored information such as a program, data or the like in an information processing apparatus such as small type of portable computer or the like. The information protective device comprises a prohibition condition storing portion, which stores the writing prohibition condition to a storage unit for programs, data or the like, and a prohibition condition setting means, which carries out the writing of prohibition instructions to be stored in the storing portion to set the writing prohibition condition, so that the storage unit may be handled like so-called read only memory (ROM), whereby the storing contents may be protected more positively.

Abstract: An electronic apparatus such as a compact computer stores a certain set of information which is useful in its operation such as a list of character codes and corresponding characters or the names of commands that can be used and the methods of using them. Such information can be displayed by entering a specified command or a character string with one or more characters, including a help requesting key.

Abstract: A silver halide color photographic material having at least one silver halide emulsion layer on a support is disclosed. Said silver halide emulsion layer contains at least one of the 1H-pyrazolo [3,2-c]-S-triazole derived magenta couplers that have a substituent of the following formula at 3-position:--R.sub.1 --S(O).sub.n --R.sub.2whereinR.sub.1 is an alkylene group;R.sub.2 is an alkyl, cycloalkyl or aryl group; andn is 1 or 2.

Abstract: A programmable calculator using at least one exchangeable reloadable memory module includes a connector for connecting the exchangeable reloadable memory module to the calculator. The calculator judges whether a program including information to execute said program is present in said exchangeable reloadable memory module, and inhibits erasure of the information to execute the program when presence of the program in the exchangeable reloadable memory module is judged by the calculator at the time of initialization of the programmable calculator.

Abstract: A text compiling device includes a first memory area for storing an intervening code program in which a statement or comment is given by a code. The intervening code is read out and is converted to an ASCII code program. The converted ASCII code program is stored in a second memory area, which partly overlaps with the first memory area. Similarly, a reverse conversion can be carried out.