Patents by Inventor Koichi Ishimi
Koichi Ishimi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11750210Abstract: The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.Type: GrantFiled: May 13, 2021Date of Patent: September 5, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koichi Ishimi, Akio Fujii
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Publication number: 20210384917Abstract: The present invention is to reduce detection of an erroneous edge caused by variation in a case of a sampling frequency that is not larger than a data transmission frequency. A semiconductor device includes: a data reception circuit configured to receive first data at first time and receive second data at second time; and an edge recognition circuit configured to set a range and detect an edge contained in the range. The edge recognition circuit includes a measurement circuit configured to measure a first period taken from the reception of the first data to the reception of the second data, and is configured to determine the range in which the edge contained in the data that is received by the data reception circuit is detected, on the basis of the first period.Type: ApplicationFiled: May 13, 2021Publication date: December 9, 2021Inventors: Koichi ISHIMI, Akio FUJII
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Patent number: 10936702Abstract: A license managing method including an execution device that executes software and a software storage device coupled to the execution device further includes a license storage device that stores license information indicating the number of licenses for permitting a license of the software, and the license managing method includes the step of license-managing of controlling storage of the software to be downloaded into the software storage device or execution of the software by the execution device based on the license information stored in the license storage device when the software whose license permission is required is downloaded.Type: GrantFiled: August 26, 2015Date of Patent: March 2, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Koichi Ishimi, Atsushi Wakao, Takashi Nakatani
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Patent number: 10372654Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: GrantFiled: January 25, 2017Date of Patent: August 6, 2019Assignee: Renesas Electronics CorporationInventor: Koichi Ishimi
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Publication number: 20180181726Abstract: A license managing method including an execution device that executes software and a software storage device coupled to the execution device further includes a license storage device that stores license information indicating the number of licenses for permitting a license of the software, and the license managing method includes the step of license-managing of controlling storage of the software to be downloaded into the software storage device or execution of the software by the execution device based on the license information stored in the license storage device when the software whose license permission is required is downloaded.Type: ApplicationFiled: August 26, 2015Publication date: June 28, 2018Inventors: Koichi ISHIMI, Atsushi WAKAO, Takashi NAKATANI
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Publication number: 20180167090Abstract: It is possible to utilize a system with a long response time using electricity generated by each generator of each communication unit. Communication units 20 and 30 include generators 21 and 31 for generating electricity utilizing a predetermined action included in a series of actions, and wireless communication circuits 24 and 34 operated by electricity supplied from the generators, respectively. The generator 21 generates electricity utilizing a certain action included in the series of actions, and the wireless communication circuit 24 transmits a signal to an external service server 70 when the certain action is done and the generator 21 generates electricity. The generator 31 generates electricity utilizing another action which is performed later in the series of actions, the wireless communication circuit 34 transmits a signal to the external service server 70 when that action is done and the generator 31 generates electricity.Type: ApplicationFiled: October 29, 2017Publication date: June 14, 2018Inventors: Koichi ISHIMI, Yuichiro TANAKA
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Publication number: 20170132167Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Inventor: Koichi ISHIMI
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Publication number: 20170091429Abstract: A license management method of performing license management using an execution unit that executes software and a software storage unit coupled to the execution unit includes the step of controlling execution of software that is stored in the software storage unit and on which a license is granted with a term being limited by the execution unit on the basis of term information that indicates the term by using a license management unit that controls execution of the software.Type: ApplicationFiled: August 11, 2016Publication date: March 30, 2017Inventors: Koichi ISHIMI, Masaya KITAO
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Publication number: 20160003910Abstract: The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor inducts a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU #0 determines if a module proximate to a delay monitor suffers from aged deterioration, based on the delay time measured by the delay monitor.Type: ApplicationFiled: September 11, 2015Publication date: January 7, 2016Inventor: Koichi ISHIMI
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Patent number: 9157959Abstract: The disclosed invention provides a semiconductor device that enables early discovery of a sign of aged deterioration that occurs locally. An LSI has a plurality of modules and a delay monitor cluster including a plurality of delay monitors. Each delay monitor includes a ring oscillator having a plurality of gate elements. Each delay monitor measures a delay time of the gate elements. A CPU #0 determines if a module proximate to a delay monitor suffers from aged deterioration, based on the delay time measured by the delay monitor.Type: GrantFiled: October 22, 2012Date of Patent: October 13, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Koichi Ishimi
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Publication number: 20140101353Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: ApplicationFiled: December 11, 2013Publication date: April 10, 2014Applicant: Renesas Electronics CorporationInventor: Koichi ISHIMI
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Patent number: 8621127Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: GrantFiled: May 15, 2012Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventor: Koichi Ishimi
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Publication number: 20120226847Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: ApplicationFiled: May 15, 2012Publication date: September 6, 2012Inventor: Koichi ISHIMI
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Patent number: 8200878Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: GrantFiled: January 8, 2008Date of Patent: June 12, 2012Assignee: Renesas Electronics CorporationInventor: Koichi Ishimi
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Publication number: 20080282012Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.Type: ApplicationFiled: January 8, 2008Publication date: November 13, 2008Inventor: Koichi ISHIMI
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Patent number: 7405607Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.Type: GrantFiled: May 15, 2007Date of Patent: July 29, 2008Assignee: Renesas Technology Corp.Inventor: Koichi Ishimi
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Publication number: 20070216462Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.Type: ApplicationFiled: May 15, 2007Publication date: September 20, 2007Applicant: Renesas Technology Corp.Inventor: Koichi Ishimi
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Patent number: 7233186Abstract: A clock generation circuit receives a reference clock signal for outputting clock signals to peripheral circuits. A duty ratio of at least one of output buffer signals output from buffer circuits included in the clock generation circuit is varied so that a duty ratio of at least one of the clock signals can be varied.Type: GrantFiled: October 10, 2003Date of Patent: June 19, 2007Assignee: Renesas Technology Corp.Inventor: Koichi Ishimi
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Patent number: 6937082Abstract: A multiplication circuit and a phase synchronization circuit as components of a digital PLL circuit adjust an oscillation frequency and a phase, respectively, of a multiplied clock by adjusting a count value of a digital counter. A CPU sets a count value for oscillating an oscillation circuit of the multiplication circuit at a frequency which is the same as that of a reference clock or is a multiple of the frequency of the reference clock in a digital counter of the multiplication circuit in accordance with a program set by the user of the information processing apparatus, and sets a count value for synchronizing the phase of an output clock with the phase of the reference clock in a digital counter of the phase synchronization circuit.Type: GrantFiled: August 25, 2003Date of Patent: August 30, 2005Assignee: Renesas Technology Corp.Inventor: Koichi Ishimi
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Publication number: 20050093593Abstract: A technique for generating an appropriate clock is provided. A clock generation circuit generates a logic-circuit clock on the basis of a reference clock and outputs the logic-circuit clock to a logic circuit. The clock generation circuit and the logic circuit are both supplied with power from a power supplier. According to a control signal from a power controller, the power supplier changes a power voltage value provided to the clock generation circuit and the logic circuit. The control signal is generated by the power controller on the basis of a counter value from the clock generation circuit. The counter value is obtained from a digital counter which determines the delay speeds of delay elements in a multiplier circuit in the clock generation circuit.Type: ApplicationFiled: October 27, 2004Publication date: May 5, 2005Inventors: Fumitaka Fukuzawa, Koichi Ishimi