Patents by Inventor Koichi Iwao

Koichi Iwao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit, method of testing the semiconductor integrated circuit, and semiconductor substrate
    Patent number: 11774493
    Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: October 3, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Koichi Iwao, Eiki Aoyama
  • SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD OF TESTING THE SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR SUBSTRATE
    Publication number: 20220317180
    Abstract: A semiconductor integrated circuit inputs and outputs signals regarding a test using two terminals, having a bidirectional terminal for input and output of data and an input terminal for input of a clock signal. A signal is output via the bidirectional terminal in accordance with an output control signal output from an output control circuit. The output control circuit performs control in synchronization with the clock signal to prevent data input to the bidirectional terminal and an output permission signal based on the output control signal from overlapping each other.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 6, 2022
    Inventors: Koichi Iwao, Eiki Aoyama
  • Inspection apparatus, image sensing apparatus, electronic equipment, and transportation equipment
    Patent number: 10650905
    Abstract: An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Iwao
  • INSPECTION APPARATUS, IMAGE SENSING APPARATUS, ELECTRONIC EQUIPMENT, AND TRANSPORTATION EQUIPMENT
    Publication number: 20190198129
    Abstract: An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 27, 2019
    Inventor: Koichi Iwao