Abstract: A power supply device performs grid connected operation and autonomous operation. The grid connected operation is operation in which power is supplied from an AC power network and a DC power source to a load. The autonomous operation is operation in which the power supply device is disconnected from the AC power network and power is supplied from the DC power source to the load. The power supply device includes a power inverter configured to receive a DC power supplied from the DC power source and output an AC power, an operation mode switching unit configured to switch between grid connected operation and autonomous operation, and an output information control unit configured to control output information about the AC power output from the power inverter.

Abstract: A backlight device includes a housing, a light source, a diffuse plate and a fixing member. The housing has an open surface. The light source is arranged in the housing. The diffuser plate is arranged on the open surface of the housing and allows light emitted from the light source to pass therethrough while diffusing the light. The fixing member prevents the diffuser plate from bending in a direction in which light passes through the diffuser plate. A part of the fixing member has transmittance adjusted to substantially equalize luminance distribution of light passed through the diffuser plate.

Abstract: A backlight device includes a housing, a light source, a diffuse plate and a fixing member. The housing has an open surface. The light source is arranged in the housing. The diffuser plate is arranged on the open surface of the housing and allows light emitted from the light source to pass therethrough while diffusing the light. The fixing member prevents the diffuser plate from bending in a direction in which light passes through the diffuser plate. A part of the fixing member has transmittance adjusted to substantially equalize luminance distribution of light passed through the diffuser plate.

Abstract: In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal (s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the fir

Abstract: In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal(s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the firs

Abstract: A backlight device includes a housing, a light source, a diffuse plate and a fixing member. The housing has an open surface. The light source is arranged in the housing. The diffuser plate is arranged on the open surface of the housing and allows light emitted from the light source to pass therethrough while diffusing the light. The fixing member prevents the diffuser plate from bending in a direction in which light passes through the diffuser plate. A part of the fixing member has transmittance adjusted to substantially equalize luminance distribution of light passed through the diffuser plate.

Abstract: A semiconductor memory device includes a memory cell provided at each of intersections of word lines and bit lines and connected to the corresponding word line and the corresponding bit line; an address transition detection circuit; an address latch circuit; an address decoder; a pre-charging circuit; and a control signal generation circuit. The address latch circuit is controlled by a bit line pre-charging signal, such that while the bit line pre-charging signal is at a first logic level, the address signal is input to the address latch circuit, and while the bit line pre-charging signal is at a second logic level, the input address signal is maintained by the address latch circuit. The address decoder is activated by the decoder activating signal. The address decoder is activated, the word line corresponding to the address signal is activated, and the memory cell connected to the corresponding word line is accessed.

Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.

Abstract: A manufacturing method of a printed circuit board is composed of a first process of forming a pattern of lower electrode 4a at a specific portion on a substrate 2 in which a capacitor element 16 is formed, a second process of forming a capacitor insulative layer 6 that is constituted by a paste material having high permittivity selectively at a position that corresponds to the lower electrode 4a, a third process of forming an interlayer insulative film 8 having low permittivity all over the entire surface of the substrate 2 including the capacitor insulative layer 6, a fourth process of exposing the capacitor insulative layer 6 by grinding the surface of the interlayer insulative film 8 so as to be flat, and a fifth process of forming a capacitor element 16 by forming a pattern of upper electrode on the surface of the capacitor insulative layer 6. Accordingly, the printed circuit board is excellent in mechanical strength, low in manufacturing cost and high in reliability and capacitance accuracy.

Abstract: A semiconductor memory device includes a memory cell provided at each of intersections of word lines and bit lines and connected to the corresponding word line and the corresponding bit line; an address transition detection circuit; an address latch circuit: an address decoder; a pre-charging circuit; and a control signal generation circuit. The address latch circuit is controlled by a bit line pre-charging signal, such that while the bit line pre-charging signal is at a first logic level, the address signal is input to the address latch circuit, and while the bit line pre-charging signal is at a second logic level, the input address signal is maintained by the address latch circuit. The address decoder is activated by the decoder activating signal. The address decoder is activated, the word line corresponding to the address signal is activated, and the memory cell connected to the corresponding word line is accessed.

Abstract: The present invention provides a thin film capacitance element having minimal deviation of capacitance value in a high accuracy formed on a printed circuit board (core material). The thin film capacitance element formed on a printed circuit board is composed of a lower electrode layer formed on the printed circuit board through an insulation layer, a dielectric layer formed on the lower electrode layer, an upper electrode layer formed on the dielectric layer and an electric pad for leading out the lower electrode layer, wherein the lower electrode layer is longer than the upper electrode layer in the horizontal direction and connected to the electric pad for leading out the lower electrode layer outside, and wherein the top surface of the upper electrode layer and the top surface of the electric pad for leading out the lower electrode layer are formed substantially in the same height.

Abstract: An optical filter, for absorbing a part of the optical signals with a central wavelength .lambda. and restricting the intensity of the transmitted light, includes a dielectric block with a high refractive index, a metal film, and a dielectric block with a low refractive index deposited on a substrate in that order in the direction of the incident light.

Abstract: An optical filter, which has a predetermined transmittance and a low reflectance at a wavelength .lambda. of, for example, 780 nm, comprises a metal film and a dielectric thin-film deposited adjacent to the metal film, the dielectric thin-film having a refractive index lower than that of the metal film and a thickness of .lambda./40 or less. Also disclosed is an optical filter, comprising a substrate, a plurality of sets of dielectric thin-films (H) with a high refractive index and dielectric thin-films (L) with a low refractive index, and a metal layer. The dielectric thin-films (H) and the dielectric thin-films (L) are alternately deposited on the substrate and the metal film is provided between one dielectric thin-film (H) and the adjacent dielectric thin-film(L). The dielectric thin-film (L) adjacent to the metal film has a thickness .lambda./40 or less.