Patents by Inventor Koichi Kanaya

Koichi Kanaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11486833
    Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: November 1, 2022
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro Sakurada, Makoto Kobayashi, Takeshi Kobayashi, Koichi Kanaya
  • Publication number: 20200240929
    Abstract: A method evaluates an edge shape of a silicon wafer, in which as shape parameters in a wafer cross section, when defining a radial direction reference L1, a radial direction reference L2, an intersection point P1, a height reference plane L3, h1 [?m], h2 [?m], a point Px3, a straight line Lx, an angle ?x, a point Px0, ? [?m], a point Px1, and a radius Rx [?m], the edge shape of the silicon wafer is measured, values of the shape parameters h1, h2, and ? are set, the shape parameters Rx and ?x are calculated in accordance with the definition based on measurement data of the edge shape, and the edge shape of the silicon wafer is determined from the calculated Rx and ?x to be evaluated. Consequently, a method evaluates an edge shape of a silicon wafer capable of preventing an occurrence of trouble.
    Type: Application
    Filed: July 27, 2018
    Publication date: July 30, 2020
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Masahiro SAKURADA, Makoto KOBAYASHI, Takeshi KOBAYASHI, Koichi KANAYA
  • Patent number: 8287331
    Abstract: There is disclosed a method for manufacturing a polishing pad that is formed of a urethane foam pad and attached to a turn table to polish a wafer, the method comprising at least steps of: slicing a urethane foam cake to provide the urethane foam pad; and performing press processing with respect to the urethane foam pad with a pressure of 15000 g/cm2 or above, a polishing pad manufactured by this method, and a method for polishing a wafer by using this polishing pad. There can be provided a method for manufacturing a polishing pad that can stably obtain a wafer with high flatness, etc.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: October 16, 2012
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koichi Kanaya, Masayoshi Sekizawa, Naotaka Toyama
  • Patent number: 7779554
    Abstract: The present invention provides a strip-like holding gripper which holds a semiconductor wafer when measuring a shape of the semiconductor wafer, wherein a side where the semiconductor wafer is held has a round shape, a groove which holds an edge of the semiconductor wafer along a side surface of the round shape portion is provided on the side surface, and the groove comes into contact with the edge of the semiconductor wafer from a periphery of the wafer to hold the semiconductor wafer. As a result, it is possible to provide the gripper, which can stably hold the wafer in a fixed state even if the gripper is inclined when holding the wafer, a holding method, and a shape measuring apparatus.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: August 24, 2010
    Assignees: Shin-Etsu Handotai Co., Ltd., Japan ADE. Ltd.
    Inventors: Masato Onishi, Koichi Kanaya
  • Patent number: 7615116
    Abstract: In a vapor phase growth apparatus including a reaction chamber, a susceptor, a lift pin, an upper heating device, and a lower heating device, a heating ratio between the upper heating ratio and the lower heating ratio is adjusted.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 10, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Koichi Kanaya, Tsuyoshi Nishizawa
  • Publication number: 20090252942
    Abstract: The present invention provides a method for manufacturing an epitaxial wafer by supplying a raw material gas onto a silicon wafer to perform vapor-phase growth of an epitaxial layer, wherein a thickness of the epitaxial layer that is formed at a peripheral portion of the silicon wafer is controlled by controlling a growth rate and/or a growth temperature of the epitaxial layer that is subjected to vapor-phase growth. As a result, there is provided the method that enables manufacturing an epitaxial wafer having a small roll-off value by controlling a thickness of an epitaxial layer near the outermost periphery at the time of epitaxial growth.
    Type: Application
    Filed: October 25, 2006
    Publication date: October 8, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koichi Kanaya, Masato Ohnishi
  • Patent number: 7591908
    Abstract: In a vapor phase growth apparatus for performing a vapor phase growth of a silicon epitaxial layer on a main surface of a silicon single crystal substrate while heating the silicon single crystal substrate placed on a pocket formed on a susceptor, from both sides, the pocket has an outer peripheral side part which supports a rear surface of the silicon single crystal substrate and an inner peripheral side part which is kept in a state of being more recessed than the outer peripheral side part in the inside of the outer peripheral side part, and the susceptor has a warped inverted U-shaped longitudinal sectional shape.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: September 22, 2009
    Assignee: Shin-Etsu Handotai Co., Ltd
    Inventors: Koichi Kanaya, Toru Otsuka, Takao Kanno
  • Publication number: 20090039581
    Abstract: The present invention provides a strip-like holding gripper which holds a semiconductor wafer when measuring a shape of the semiconductor wafer, wherein a side where the semiconductor wafer is held has a round shape, a groove which holds an edge of the semiconductor wafer along a side surface of the round shape portion is provided on the side surface, and the groove comes into contact with the edge of the semiconductor wafer from a periphery of the wafer to hold the semiconductor wafer. As a result, it is possible to provide the gripper, which can stably hold the wafer in a fixed state even if the gripper is inclined when holding the wafer, a holding method, and a shape measuring apparatus.
    Type: Application
    Filed: March 9, 2006
    Publication date: February 12, 2009
    Applicants: SHIN-ETSU HANDOTAI CO., LTD., JAPAN ADE LTD.
    Inventors: Masato Onishi, Koichi Kanaya
  • Patent number: 7459720
    Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of ? (0°<?<90°) for the [011] direction, ? (0°<?<90°) for the [01-1] direction and ? (0°??<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: December 2, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Tatsuo Ito, Koichi Kanaya
  • Publication number: 20080248728
    Abstract: There is disclosed a method for manufacturing a polishing pad that is formed of a urethane foam pad and attached to a turn table to polish a wafer, the method comprising at least steps of: slicing a urethane foam cake to provide the urethane foam pad; and performing press processing with respect to the urethane foam pad with a pressure of 15000 g/cm2 or above, a polishing pad manufactured by this method, and a method for polishing a wafer by using this polishing pad. There can be provided a method for manufacturing a polishing pad that can stably obtain a wafer with high flatness, etc.
    Type: Application
    Filed: April 1, 2008
    Publication date: October 9, 2008
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koichi Kanaya, Masayoshi Sekizawa, Naotaka Toyama
  • Publication number: 20070119367
    Abstract: In a vapor phase growth apparatus including a reaction chamber, a susceptor, a lift pin, an upper heating device, and a lower heating device, a heating ratio between the upper heating ratio and the lower heating ratio is adjusted.
    Type: Application
    Filed: September 27, 2004
    Publication date: May 31, 2007
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Koichi Kanaya, Tsuyoshi Nishizawa
  • Publication number: 20060180076
    Abstract: In a vapor phase growth apparatus for performing a vapor phase growth of a silicon epitaxial layer on a main surface of a silicon single crystal substrate while heating the silicon single crystal substrate placed on a pocket formed on a susceptor, from both sides, the pocket has an outer peripheral side part which supports a rear surface of the silicon single crystal substrate and an inner peripheral side part which is kept in a state of being more recessed than the outer peripheral side part in the inside of the outer peripheral side part, and the susceptor has a warped inverted U-shaped longitudinal sectional shape.
    Type: Application
    Filed: April 26, 2004
    Publication date: August 17, 2006
    Applicant: Shin-Etsu Handotal Co., Ltd.
    Inventors: Koichi Kanaya, Toru Otsuka, Takao Kanno
  • Publication number: 20060180086
    Abstract: A susceptor (2) in which a semiconductor substrate (W) is supported approximately horizontally in a pocket (2c) when performing a vapor phase growth of a single crystal thin film on a front surface of the semiconductor substrate (W), and in which the pocket (2c) comprises an outer peripheral pocket portion (20) to support the semiconductor substrate (W) and a central side pocket portion (21) which is formed inside the outer peripheral side pocket portion (20) to be concave from the outer peripheral side pocket portion (20), wherein the outer peripheral side pocket portion (20) comprises a substrate supporting surface (20a) which is inclined with respect to a horizontal surface to be lowered toward a central side from an outer peripheral side of the pocket (2c), and a region of the substrate supporting surface (20a) excluding at least an inner peripheral edge supports a portion of a rear surface of the semiconductor substrate (W) which is inside an outer peripheral edge of the semiconductor substrate (W).
    Type: Application
    Filed: March 12, 2004
    Publication date: August 17, 2006
    Applicant: SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Koichi Kanaya, Toru Otsuka, Igroki Ose
  • Patent number: 6958094
    Abstract: The present invention provides a method for slicing a single crystal, wherein the single crystal is sliced by irradiating a portion to be sliced with an ultra short pulse laser beam while supplying a gas containing gaseous molecules or radicals that react with atoms constituting the single crystal to become stable gaseous molecules in the vicinity of the portion under slicing. Thus, there is provided a method for slicing a single crystal by using a laser processing, in which a single crystal is processed while obtaining a good sliced surface and markedly reducing a slicing loss.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: October 25, 2005
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Toshikuni Shinohara, Tatsuo Ito, Koichi Kanaya
  • Publication number: 20030160304
    Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of &agr; (0°<&agr;<90°) for the [011] direction, &bgr; (0°<&bgr;<90°) for the [01-1] direction and &ggr; (0°≦&ggr;<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.
    Type: Application
    Filed: January 8, 2003
    Publication date: August 28, 2003
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Tatsuo Ito, Koichi Kanaya
  • Publication number: 20030155335
    Abstract: The present invention provides a method for slicing a single crystal, wherein the single crystal is sliced by irradiating a portion to be sliced with an ultra short pulse laser beam while supplying a gas containing gaseous molecules or radicals that react with atoms constituting the single crystal to become stable gaseous molecules in the vicinity of the portion under slicing. Thus, there is provided a method for slicing a single crystal by using a laser processing, in which a single crystal is processed while obtaining a good sliced surface and markedly reducing slicing loss.
    Type: Application
    Filed: January 8, 2003
    Publication date: August 21, 2003
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Toshikuni Shinohara, Tatsuo Ito, Koichi Kanaya
  • Patent number: 6217651
    Abstract: In the process of thin film growth, actual temperature of a substrate is measured and corrected with low cost in short time. With first thin film growth equipment of which a difference between set temperature of a heating source and an actual temperature of the substrate (hereinafter, referred to as temperature characteristic) is known, a first calibration curve representing “thin film growth rate vs. substrate actual temperature” is prepared. Next, thin film growth is conducted at one set temperature T2 with use of second thin film growth equipment whose temperature characteristic is unknown, where a difference from a set temperature T1 reading from the first calibration curve in correspondence to a thin film growth rate G resulting from the thin film growth process is determined.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: April 17, 2001
    Assignee: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Hisashi Kashino, Koichi Kanaya
  • Patent number: 5784663
    Abstract: A control system for collectively supervising a plurality of copiers or similar image forming apparatuses connected to a control device by communication lines with or without the intermediary of communication control units. To down-load data relating to image formation, the control device determines whether or not a copier of interest is in an inoperative state and, if it is in an inoperative state, automatically sends the data to the copier via a telephone line, an exchange, and a communication control unit. This data is written to storing means built in the copier. To up-load data relating to image formation, the control device causes each copier to automatically send the data stored in the storing means and stores the data in memory means. Up-loading is effected at an optimal time other than the time when the copier is performing an automatic adjustment, is in use, or is quite likely to be used.
    Type: Grant
    Filed: March 7, 1997
    Date of Patent: July 21, 1998
    Assignee: Ricoh Company, Ltd.
    Inventors: Masayuki Hayashi, Yoshihiro Mitekura, Koichi Kanaya, Masato Terao, Toshiya Tagawa, Nobuaki Tomidokoro, Masahiro Kitayama, Osamu Kizaki, Yasuo Kawada, Kazuyuki Nakahara, Tomofumi Harada, Yasunari Hashimoto
  • Patent number: 5694201
    Abstract: A control system for collectively supervising a plurality of copiers or similar image forming apparatuses connected to a control device by communication lines with or without the intermediary of communication control units. To down-load data relating to image formation, the control device determines whether or not a copier of interest is an inoperative state and, if it is in an inoperative state, automatically sends the data to the copier via a telephone line, an exchange, and a communication control unit. This data is written to storing means built in the copier. To up-load data relating to image formation, the control device causes each copier to automatically send the data stored in the storing means thereof and stores the data in memory means thereof. Up-loading is effected at an optimal time other than the time when the copier is performing an automatic adjustment, in use, or quite likely to be used.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: December 2, 1997
    Assignee: Ricoh Company, Ltd.
    Inventors: Masayuki Hayashi, Yoshihiro Mitekura, Koichi Kanaya, Masato Terao, Toshiya Tagawa, Nobuaki Tomidokoro, Masahiro Kitayama, Osamu Kizaki, Yasuo Kawada, Kazuyuki Nakahara, Tomofumi Harada, Yasunari Hashimoto
  • Patent number: 5571333
    Abstract: A heat treatment furnace has a reaction tube with one open end and a detachable front cap with an exhaust port provided such that it closes the opening of the reaction tube. A detachable inner tube is provided in an opening of the reaction tube wherein the inner tube has a cylindrical side whose diameter is smaller than the inner diameter of the reaction tube. A disk-shaped end is located such that there is a space between the disk-shaped end and the front cap and it has a through hole(s).
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: November 5, 1996
    Assignee: Shin-Etsu Handotai Co. Ltd.
    Inventor: Koichi Kanaya