Patents by Inventor Koichi Kanryo

Koichi Kanryo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10546691
    Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki Inoue, Takeo Arakawa, Kensuke Aoki, Hiromasa Saeki, Koichi Kanryo, Akihiro Tsuru, Haruhiko Mori
  • Patent number: 10005150
    Abstract: A method for manufacturing an electronic device using ultrasonic joining, when the component members of the electronic device includes different structures. The method includes obtaining a joining condition that provides press-down amounts for the materials to be joined at predetermined values. The press-down amount generated by a horn and a supporting member biting into the materials during ultrasonic joining is predetermined for each specific structure of the component member of the electronic device.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 26, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Koichi Kanryo, Hiroki Endo, Hideyuki Fujiki
  • Publication number: 20180158610
    Abstract: A capacitor that includes a conductive base material with high specific surface area, a dielectric layer covering the conductive base material with high specific surface area, and an upper electrode covering the dielectric layer, in which the conductive base material with high specific surface area is formed of a metal sintered body as a whole.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 7, 2018
    Inventors: NORIYUKI INOUE, Takeo Arakawa, Kensuke Aoki, Hiromasa Saeki, Koichi Kanryo, Akihiro Tsuru, Haruhiko Mori
  • Publication number: 20180047517
    Abstract: A capacitor that includes a conductive metal base material with a porous part, a dielectric layer on the porous part, and an upper electrode on the dielectric layer, and has an electrostatic capacitance formation part only on one principal surface side of the capacitor.
    Type: Application
    Filed: October 5, 2017
    Publication date: February 15, 2018
    Inventors: KOICHI KANRYO, Noriyuki Inoue, Hiromasa Saeki, Takeo Arakawa, Kazuo Hattori, Ken Ito
  • Patent number: 9865400
    Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 ?m or more at ½ of a depth of the at least one groove.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ken Ito, Noriyuki Inoue, Koichi Kanryo
  • Patent number: 9756718
    Abstract: A module board includes a base substrate. Electronic components are mounted on a first principal surface of the base substrate. The mounted electronic components are sealed by a sealing resin containing an SiO2 filler. A top surface and side surfaces of the sealing resin are covered with a shield layer containing a carbon filler, which is flat powder, as a conductive component. A terminal electrode is formed on a second principal surface of the base substrate that is disposed opposite to the first principal surface of the base substrate.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: September 5, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuji Kataoka, Koichi Kanryo
  • Publication number: 20170018368
    Abstract: A capacitor that includes a conductive porous base material; a dielectric layer; and an electrode. The conductive porous base material, the dielectric layer, and the upper electrode are laminated together to constitute an effective part that accumulates charges in the dielectric layer when a voltage is applied between the conductive porous base material and the electrode. The conductive porous base material includes at least one groove having a width of 10 ?m or more at ½ of a depth of the at least one groove.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 19, 2017
    Inventors: Ken Ito, Noriyuki Inoue, Koichi Kanryo
  • Patent number: 9408311
    Abstract: A method of manufacturing an electronic component module includes sealing a surface of an aggregate substrate on which a plurality of electronic components are mounted with a sealing resin and cutting boundary portions between electronic component modules from an outer surface of the sealing resin to a position at least partially through the aggregate substrate to form first grooves. A shield layer is formed by coating the outer surface of the sealing resin with a conductive resin and filling the first grooves with the conductive resin, and recesses are formed at positions on the shield layer where the first grooves are formed. The boundary portions between electronic component modules are cut along the corresponding recesses so that second grooves each having a width smaller than the width of a corresponding one of the recesses are formed, and the aggregate substrate is singulated into the individual electronic component modules.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: August 2, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Kanryo, Akio Katsube, Shunsuke Kitamura
  • Publication number: 20150136839
    Abstract: A method for manufacturing an electronic device using ultrasonic joining, when the component members of the electronic device includes different structures. The method includes obtaining a joining condition that provides press-down amounts for the materials to be joined at predetermined values. The press-down amount generated by a horn and a supporting member biting into the materials during ultrasonic joining is predetermined for each specific structure of the component member of the electronic device.
    Type: Application
    Filed: January 30, 2015
    Publication date: May 21, 2015
    Inventors: KOICHI KANRYO, Hiroki Endo, Hideyuki Fujiki
  • Publication number: 20140204550
    Abstract: A module board includes a base substrate. Electronic components are mounted on a first principal surface of the base substrate. The mounted electronic components are sealed by a sealing resin containing an SiO2 filler. A top surface and side surfaces of the sealing resin are covered with a shield layer containing a carbon filler, which is flat powder, as a conductive component. A terminal electrode is formed on a second principal surface of the base substrate that is disposed opposite to the first principal surface of the base substrate.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 24, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yuji Kataoka, Koichi Kanryo
  • Publication number: 20130294034
    Abstract: A method of manufacturing an electronic component module includes sealing a surface of an aggregate substrate on which a plurality of electronic components are mounted with a sealing resin and cutting boundary portions between electronic component modules from an outer surface of the sealing resin to a position at least partially through the aggregate substrate to form first grooves. A shield layer is formed by coating the outer surface of the sealing resin with a conductive resin and filling the first grooves with the conductive resin, and recesses are formed at positions on the shield layer where the first grooves are formed. The boundary portions between electronic component modules are cut along the corresponding recesses so that second grooves each having a width smaller than the width of a corresponding one of the recesses are formed, and the aggregate substrate is singulated into the individual electronic component modules.
    Type: Application
    Filed: July 5, 2013
    Publication date: November 7, 2013
    Inventors: Koichi KANRYO, Akio KATSUBE, Shunsuke KITAMURA
  • Patent number: 8016184
    Abstract: A method for manufacturing an electronic component module is performed such that a shield layer can be formed as a thin film and an electronic component can be effectively shielded. A collective substrate including a plurality of electronic component modules including a plurality of electronic components is batch-sealed with a resin. A cut section is formed from a top surface of the sealed resin to a position that reaches a grounding electrode arranged in the substrate at a boundary section of the electronic component module so as to expose the grounding electrode. A conductive paste is applied on side surfaces and the top surface. Then, a conductive thin film is formed by spin coating, and the electronic component module is cut.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: September 13, 2011
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koichi Kanryo, Akio Katsube, Akira Tanaka
  • Publication number: 20110006106
    Abstract: A method for manufacturing an electronic component module is performed such that a shield layer can be formed as a thin film and an electronic component can be effectively shielded. A collective substrate including a plurality of electronic component modules including a plurality of electronic components is batch-sealed with a resin. A cut section is formed from a top surface of the sealed resin to a position that reaches a grounding electrode arranged in the substrate at a boundary section of the electronic component module so as to expose the grounding electrode. A conductive paste is applied on side surfaces and the top surface. Then, a conductive thin film is formed by spin coating, and the electronic component module is cut.
    Type: Application
    Filed: September 22, 2010
    Publication date: January 13, 2011
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Koichi KANRYO, Akio KATSUBE, Akira TANAKA
  • Patent number: 6437412
    Abstract: A surface acoustic wave device includes a surface acoustic wave element and a package. The package has a base member and a conductive cap member which are joined together by a sealing material so as to hermetically seal the surface acoustic wave element therein. The conductive cap member is coated with the sealing material on the entire surface thereof that is disposed opposite to the base member.
    Type: Grant
    Filed: June 12, 2000
    Date of Patent: August 20, 2002
    Assignee: Murata Manufacturing Co. Ltd.
    Inventors: Masato Higuchi, Atsushi Hirakawa, Shinobu Uesugi, Koichi Kanryo