Patents by Inventor Koichi Katou

Koichi Katou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cache memory analyzing method
    Patent number: 7590792
    Abstract: It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address contained in the information are totalized. The cache miss generated addresses whose generated cache miss numbers are totalized are sectionalized by each of the sets. Further, the address group whose numbers of cache miss generated are consistent or close is extracted from a plurality of cache miss generated addresses divided as addresses in the same set.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: September 15, 2009
    Assignee: Panasonic Corporation
    Inventors: Masumi Yamaga, Takanori Miyashita, Koichi Katou
  • Cache memory analyzing method
    Publication number: 20070055809
    Abstract: It is done to read information containing an address of a memory at which a cache miss is generated, from a cache memory. The numbers of cache misses generated at each cache miss generated address contained in the information are totalized. The cache miss generated addresses whose generated cache miss numbers are totalized are sectionalized by each of the sets. Further, the address group whose numbers of cache miss generated are consistent or close is extracted from a plurality of cache miss generated addresses divided as addresses in the same set.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Inventors: Masumi Yamaga, Takanori Miyashita, Koichi Katou