Abstract: A central processing unit which achieves increased processing speed is provided. In a CPU constituted of a RISC architecture, a program counter which indicates an address in an instruction memory and a general-purpose register which is designated as an operand in an instruction to be decoded by an instruction decoder are constituted of asynchronous storage elements.

Abstract: Two or more cores (2a, 2b) in each of which two more types of passage layers through which two or more fluids flow are layered alternately are welded together. The entire bottom portions of the cores (2a, 2b) are covered with a lower header tank (3), thereby making the fluids flow into the cores (2a, 2b). A dummy layer (14) through which none of the fluids flow is provided beside a weld side face of each core (2a, 2b). A weld spacer (18) is welded to the entire peripheral edge of a side plate (16) of the dummy layer (14). A through-hole (16a) for draining water in the dummy layer (14) is made near the lower end of the side plate of the dummy layer (14). Further, a liquid drain hole (20) through which water is drained is made at a lower corner of the weld spacer (18).

Abstract: Two or more cores (2a, 2b) in each of which two more types of passage layers through which two or more fluids flow are layered alternately are welded together. The entire bottom portions of the cores (2a, 2b) are covered with a lower header tank (3), thereby making the fluids flow into the cores (2a, 2b). A dummy layer (14) through which none of the fluids flow is provided beside a weld side face of each core (2a, 2b). A weld spacer (18) is welded to the entire peripheral edge of a side plate (16) of the dummy layer (14). A through-hole (16a) for draining water in the dummy layer (14) is made near the lower end of the side plate of the dummy layer (14). Further, a liquid drain hole (20) through which water is drained is made at a lower corner of the weld spacer (18).

Abstract: A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for use in execution of this instruction information part. The program data area 38 comprises a plurality of 24-bit data areas each having an address indicative thereof. One instruction is stored in one data area such that the instruction information part resides at the beginning of the data area.

Abstract: A program data area 38 storing program data is provided in an internal memory unit that a control circuit 31 of a CPU 3 can directly red from. The program data is constituted by instructions each comprising an instruction information part and an operand (i.e., a complementary information part) for use in execution of this instruction information part. The program data area 38 comprises a plurality of 24-bit data areas each having an address indicative thereof. One instruction is stored in one data area such that the instruction information part resides at the beginning of the data area.