Patents by Inventor Koichi Kitaguro

Koichi Kitaguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6798018
    Abstract: A semiconductor device has a cell region where transistor cells of a trench structure are arranged in a matrix form, in which a recessed trench is formed in a semiconductor layer, a gate oxide film is formed inside the recessed trench, and a gate electrode formed of polysilicon is disposed inside the recessed trench. To have contact with a gate wiring formed of a metal film, a gate pad disposed continuously to the gate electrode is placed inside a recessed part formed in the same depth as the recessed trench. Consequently, many transistor cells of the trench structure are formed in a matrix form. Even in a semiconductor device where the gate wiring formed of a metal film is contacted with the gate electrode, a semiconductor device of a structure allowing gate voltage to be increased sufficiently can be obtained.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: September 28, 2004
    Assignee: Rohm Co., Ltd.
    Inventors: Masaru Takaishi, Koichi Kitaguro, Hiroki Takada
  • Publication number: 20020190313
    Abstract: A semiconductor device has a cell region where transistor cells of a trench structure are arranged in a matrix form, in which a recessed trench is formed in a semiconductor layer, a gate oxide film is formed inside the recessed trench, and a gate electrode formed of polysilicon is disposed inside the recessed trench. To have contact with a gate wiring formed of a metal film, a gate pad disposed continuously to the gate electrode is placed inside a recessed part formed in the same depth as the recessed trench. Consequently, many transistor cells of the trench structure are formed in a matrix form. Even in a semiconductor device where the gate wiring formed of a metal film is contacted with the gate electrode, a semiconductor device of a structure allowing gate voltage to be increased sufficiently can be obtained.
    Type: Application
    Filed: June 13, 2002
    Publication date: December 19, 2002
    Inventors: Masaru Takaishi, Koichi Kitaguro, Hiroki Takada
  • Patent number: 6444547
    Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: September 3, 2002
    Assignee: Rohm Co., Ltd.
    Inventors: Kazuhisa Sakamoto, Koichi Kitaguro
  • Publication number: 20020001925
    Abstract: The present invention is characterized by providing epitaxial growth of a semiconductor layer on the surface of a wafer not provided with mirror finishing and having irregularity, introducing impurities having different conductivity type in the epitaxially grown semiconductor layer to form at least a pn junction, and further providing rapid thermal anneal by rapid heating-up and rapid cooling-down in any step in the manufacturing process. By so processing, there can be obtained a semiconductor device having high speed switching characteristics in stable manner without causing problems in manufacturing process such as diffusion of heavy metal or irradiation of corpuscular ray.
    Type: Application
    Filed: December 22, 1998
    Publication date: January 3, 2002
    Inventors: KAZUHISA SAKAMOTO, KOICHI KITAGURO
  • Patent number: 6107161
    Abstract: It is an object of the present invention to provide a semiconductor chip which is hard to be damaged when the semiconductor chip is cut out from a sheet of wafer for semiconductor and a method for manufacturing thereof. Cutting grooves 26 having a wider width than scribing lines (lines for carrying out scribing) 24 which is cut by a dicing saw are formed on the upper part of the wafer 20. That is, walls 32 of the cutting grooves 26 are set back from cutting planes 30 in side walls 28 of die 22 thus cut out. So that, there is only a slight probability of contact of the dicing saw with the walls 32 of the cutting grooves 26 when the wafer 20 is cut along the center of the cutting grooves 26 with the dicing saw. As a result, it is possible to prevent chips of the upper part of the dies 22 caused by a blade of the dicing saw.
    Type: Grant
    Filed: February 6, 1998
    Date of Patent: August 22, 2000
    Assignee: Rohm Co., Ltd.
    Inventors: Koichi Kitaguro, Hiroshi Kadonishi