Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: A semiconductor integrated circuit including a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two horizontal scanning lines.

Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.

Abstract: A semiconductor integrated circuit includes a first register which latches display data, a second register which latches the display data of the first register in accordance with a first clock, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage in accordance with the display data of the second register from the plurality of gray scale voltages, and an amplifier including a first transistor, and a second transistor. A first terminal of the first transistor and a first terminal of the second transistor are connected to a first voltage line, and the gray scale voltage outputted from the decoder is supplied to one of input terminals of the first transistor and the second transistor in accordance with a control signal. A phase of the control signal is reversed at intervals of two frame periods.

Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.

Abstract: Disclosed are an electron emission thin-film with improved secondary electron emission characteristics compared with conventional ones, a plasma display panel including the electron emission thin-film, and their manufacturing methods. Using a vacuum deposition system, a protective layer that is an MgO thin-film is formed on a dielectric layer formed on a front glass substrate. At the time of deposition, angles that lines linking the central point of a target material for the protective layer respectively with the central point and both ends points of the front glass substrate form with the front glass substrate are exclusively in a range of 30 to 80°. This enables at least some of MgO columnar crystals constituting the protective layer to have flat planes that are inclined with respect to the surface of the thin-film.

Abstract: A semiconductor integrated circuit includes a first register, a second register, a gray scale voltage generator which outputs a plurality of gray scale voltages, a decoder which selects a gray scale voltage, and an amplifier including a first transistor, a second transistor, a third transistor, and a fourth transistor. A first terminal of the first transistor and a first terminal of the second transistors are connected to a first voltage line, a first terminal of the third transistor and a first terminal of the fourth transistor are connected to a second voltage line, a second terminal of the first transistor is connected to a second terminal of the third transistor, and a second terminal of the second transistor is connected to a second terminal of the fourth transistor.

Abstract: A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.

Abstract: A liquid crystal display device having a liquid crystal display element having a plurality of pixels. The video signal line driver circuit includes a plurality of amplifiers each of which has a pair of a first input terminal and a second input terminal, and a plurality of pairs of an inverting input terminal and a noninverting input terminal. Each of the plurality of amplifiers has a switching circuit which switches between a first state and a second state, based on a switching control signal supplied with a switching repetition period equal to double a display line repetition period.

Abstract: A plasma display panel having excellent electron emission properties and a method of making the same. A plasma display panel is provided with a protective layer having a dense growth of columnar crystals formed on a dielectric layer. A middle layer can be provided for improving orientation of the columnar crystals. A heating step creates seed crystals to increase the width and growth of columnar crystals with a selective orientation and greater diameter. The area of any exposed surfaces on the protective layer becomes smaller and absorption of impurities decreases. A layer of grain crystals or an amorphic crystal layer is initially deposited on the dielectric layer to establish wider area seed crystals of a desired orientation. A vacuum evaporated complimentary protective layer can then be grown with the improved configuration.

Abstract: A liquid crystal display device includes drain signal lines, gate signal lines, thin film transistors, and a drain driver. The drain driver includes an amplifier circuit having a switching circuit which switches between a first state and a second state, the first state being a state where a first input terminal of the amplifier circuit is coupled to an inverting input terminal and a second input terminal is coupled to a noninverting input terminal, and the second state being a state where the first input terminal is coupled to the noninverting input terminal and the second input terminal is coupled to the inverting input terminal. The amplifier circuit supplies signal voltages to the thin film transistors via the drain signal lines which are gray scale voltages one of plus and minus offset voltages in a first frame and in a second frame.

Abstract: A gas discharge panel capable of high-speed driving at a low drive voltage, while suppressing the occurrence of write errors in a write period, and a manufacturing method for the same. To achieve this, in the gas discharge panel of the present invention, a secondary gas formed from at least one of carbon dioxide, water vapor, oxygen and nitrogen is induced into discharge spaces 30 evacuated until the residual gas pressure is 0.02 mPa or less, and an He—Xe or Ne—Xe rare gas (discharge gas) is induced into discharge spaces 30. The amount of the secondary gas included within discharge spaces 30 when, for example, carbon dioxide is included therein, is suitably set in terms of both a discharge starting voltage and an electron emission ability, so that the partial pressure of the carbon dioxide is in a range of 0.05 mPa to 0.5 mPa inclusive.

Abstract: Disclosed are an electron emission thin-film with improved secondary electron emission characteristics compared with conventional ones, a plasma display panel including the electron emission thin-film, and their manufacturing methods. Using a vacuum deposition system, a protective layer that is an MgO thin-film is formed on a dielectric layer formed on a front glass substrate. At the time of deposition, angles that lines linking the central point of a target material for the protective layer respectively with the central point and both ends points of the front glass substrate form with the front glass substrate are exclusively in a range of 30 to 80°. This enables at least some of MgO columnar crystals constituting the protective layer to have flat planes that are inclined with respect to the surface of the thin-film.

Abstract: An electron emission thin-film with improved secondary electron emission characteristics compared with conventional ones, a plasma display panel including the electron emission thin-film, and their manufacturing methods. Using a vacuum deposition system, a protective layer that is an MgO thin-film is formed on a dielectric layer formed on a front glass substrate. At the time of deposition, angles that lines linking the central point of a target material for the protective layer respectively with the central point and both ends points of the front glass substrate form with the front glass substrate are exclusively in a range of 30 to 80 °. This enables at least some of MgO columnar crystals constituting the protective layer to have flat planes that are inclined with respect to the surface of the thinfilm.

Abstract: A liquid crystal display device having a liquid crystal display element having a plurality of pixels. The video signal line driver circuit includes a plurality of amplifiers each of which has a pair of a first input terminal and a second input terminal, and a plurality of pairs of an inverting input terminal and a noninverting input terminal. Each of the plurality of amplifiers has a switching circuit which switches between a first state and a second state, based on a switching control signal supplied with a switching repetition period equal to double a display line repetition period.

Abstract: A gas discharge panel capable of high-speed driving at a low drive voltage, while suppressing the occurrence of write errors in a write period, and a manufacturing method for the same. To achieve this, in the gas discharge panel of the present invention, a secondary gas formed from at least one of carbon dioxide, water vapor, oxygen and nitrogen is induced into discharge spaces 30 evacuated until the residual gas pressure is 0.02 mPa or less, and an He—Xe or Ne—Xe rare gas (discharge gas) is induced into discharge spaces 30. The amount of the secondary gas included within discharge spaces 30 when, for example, carbon dioxide is included therein, is suitably set in terms of both a discharge starting voltage and an electron emission ability, so that the partial pressure of the carbon dioxide is in a range of 0.05 mPa to 0.5 mPa inclusive.

Abstract: A PDP does not suffer from dielectric breakdown even though a dielectric layer is thin, with the problems of conventional PDPs, such as cracks appearing in the glass substrates during the production of the PDP being avoided. To do so, the surface of silver electrodes of the PDP is coated with a 0.1-10 &mgr;m layer of a metallic oxide, on whose surface OH groups exist, such as ZnO, ZrO2, MgO, TiO2, Al2O3, and Cr2O3. The metallic oxide layer is then coated with the dielectric layer. It is preferable to form the metallic oxide layer with the CVD method. The surface of a metallic electrode can be coated with a metallic oxide, which is then coated with a dielectric layer. The dielectric layer can be made of a metallic oxide with a vacuum process method or the plasma thermal spraying method. The dielectric layer formed on electrodes with the CVD method is remarkably thin and flawless.

Abstract: Each video signal driver circuit in a liquid crystal display device includes a first amplifier circuit with a first output terminal and first and second input terminals; a second amplifier circuit with a second output terminal and third and fourth input terminals; a first connecting circuit switchable between a first connection wherein an output voltage from the first output terminal is input to the first input terminal as a reference voltage, and a second connection wherein the output voltage from the first output terminal is input to the second input terminal as a reference voltage; and a second connecting circuit switchable between a third connection wherein an output voltage from the second output terminal is input to the third input terminal as a reference voltage, and a fourth connection wherein the output voltage from the second output terminal is input to the fourth input terminal as a reference voltage.