Patents by Inventor Koichi Koyano

Koichi Koyano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Device for sealing and cooling multi-chip modules
    Patent number: 6890799
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: May 10, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda
  • Device for sealing and cooling multi-chip modules
    Publication number: 20030103333
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Application
    Filed: January 7, 2003
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda
  • Device for sealing and cooling multi-chip modules
    Patent number: 6528878
    Abstract: According to the invention, a sealing top plate in a multi-chip module is formed from a ceramic with high thermal conductivity having a thermal expansion coefficient consistent with that of a multi-layer circuit substrate. A cooling flow path cover covering the entirety of cooling flow path grooves is formed as a separate metallic member. The back surface of the sealing top plate, on which are formed the cooling flow path grooves, is bonded directly to the back surface of a semiconductor device using solder. A thermal-conductive jacket with low thermal resistance is provided. A multi-chip module sealing frame is soldered to the edge of the sealing top plate. Furthermore, a sealing material such as an O-ring is simply interposed between the edge of the sealing top plate and the cooling water path cover, and tightening means is used to tighten the metallic cooling flow path cover and the multi-chip module sealing frame to each other.
    Type: Grant
    Filed: August 4, 2000
    Date of Patent: March 4, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Daikoku, Kenichi Kasai, Toshitada Netsu, Koichi Koyano, Takayuki Uda