Patents by Inventor Koichi Meguro
Koichi Meguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9362173Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: GrantFiled: October 18, 2011Date of Patent: June 7, 2016Assignee: Nantong Fujitsu Microelectronics Co., Ltd.Inventors: Lei Shi, Yujuan Tao, Guohua Gao, Naomi Masuda, Koichi Meguro
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Patent number: 8883627Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: GrantFiled: October 18, 2011Date of Patent: November 11, 2014Assignee: Nantong Fujitsu Microelectronics Co., Ltd.Inventors: Lei Shi, Guohua Gao, Yujuan Tao, Naomi Masuda, Koichi Meguro
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Publication number: 20130280904Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: ApplicationFiled: October 18, 2011Publication date: October 24, 2013Applicant: NANTONG FUJITSU MICROELECTRONICS CO., LTD.Inventors: Lei Shi, Guohua Gao, Yujuan Tao, Naomi Masuda, Koichi Meguro
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Publication number: 20130224910Abstract: Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield.Type: ApplicationFiled: October 18, 2011Publication date: August 29, 2013Applicant: NANTONG FUJITSU MOCROELECTRONICS CO., LTD.Inventors: Lei Shi, Yujuan Tao, Guohua Gao, Naomi Masuda, Koichi Meguro
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Publication number: 20130034934Abstract: A method for manufacturing a wafer level package is provided that enables suppressing the wearing of a cutter and extending the lifetime of the cutter, including forming insulating first resin over the top face of a substrate, which includes a groove for wiring to be formed; forming a film of first metal that is to serve as a portion of the wiring on the top face of the first resin using physical vapor deposition; forming a film of second metal that is to form a portion of the wiring on the top face of the first metal, with a lower hardness than the first metal; setting a cutter at a height corresponding to a place where the film of the first metal is not formed on a side face of the groove or the film thickness is low; and cutting at least the first resin by scanning the cutter.Type: ApplicationFiled: March 12, 2012Publication date: February 7, 2013Applicant: SK Link Co., Ltd.Inventors: Koichi MEGURO, Kanji Otsuka
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Patent number: 7056770Abstract: First, a board is placed on a board mounting portion with a lower mold and an upper mold being opened. Then, a resin material having such size and shape that correspond to the size and shape of a cavity formed in the lower mold is fitted in the cavity. Thereafter, the resin material is heated resulting in melted resin. Thereafter, the lower mold and the upper mold are closed, with a space formed by the upper mold and the lower mold being reduced in pressure. As a result, chips and wires are immersed in the melted resin. Thereafter, the melted resin is set, so that a resin mold product including the board and the set resin is formed.Type: GrantFiled: November 20, 2003Date of Patent: June 6, 2006Assignees: Towa Corporation, Fujitsu LimitedInventors: Hiroshi Uragami, Osamu Nakagawa, Kinya Fujino, Shinji Takase, Hideki Tokuyama, Koichi Meguro, Toru Nishino, Noboru Hayasaka
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Publication number: 20040101631Abstract: First, a board is placed on a board mounting portion with a lower mold and an upper mold being opened. Then, a resin material having such size and shape that correspond to the size and shape of a cavity formed in the lower mold is fitted in the cavity. Thereafter, the resin material is heated resulting in melted resin. Thereafter, the lower mold and the upper mold are closed, with a space formed by the upper mold and the lower mold being reduced in pressure. As a result, chips and wires are immersed in the melted resin. Thereafter, the melted resin is set, so that a resin mold product including the board and the set resin is formed.Type: ApplicationFiled: November 20, 2003Publication date: May 27, 2004Applicants: TOWA CORPORATION, FUJITSU LIMITEDInventors: Hiroshi Uragami, Osamu Nakagawa, Kinya Fujino, Shinji Takase, Hideki Tokuyama, Koichi Meguro, Toru Nishino, Noboru Hayasaka
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Patent number: 6673654Abstract: A semiconductor device is manufactured by an integrated circuit forming process, and a series of subsequent steps. In the series of steps, a protection tape 18 is adhered onto a first surface of a semiconductor substrate on which a plurality of semiconductor elements are formed, and the second surface of the semiconductor substrate is ground so that the semiconductor substrate has a desired thickness, the semiconductor substrate is then conveyed while controlling the temperature of the semiconductor substrate. The semiconductor substrate is then separated into a plurality of semiconductor elements. The occurrence of warping on the semiconductor substrate during conveyance of the semiconductor substrate is thus prevented.Type: GrantFiled: March 5, 2002Date of Patent: January 6, 2004Assignee: Fujitsu LimitedInventors: Takao Ohno, Koichi Meguro, Shigeru Kamada, Keisuke Fukuda, Yuzo Shimobeppu
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Publication number: 20030077879Abstract: A semiconductor device is manufactured by an integrated circuit forming process, and a series of subsequent steps. In the series of steps, a protection tape 18 is adhered onto a first surface of a semiconductor substrate on which a plurality of semiconductor elements are formed, and the second surface of the semiconductor substrate is ground so that the semiconductor substrate has a desired thickness, the semiconductor substrate is then conveyed while controlling the temperature of the semiconductor substrate. The semiconductor substrate is then separated into a plurality of semiconductor elements. The occurrence of warping on the semiconductor substrate during conveyance of the semiconductor substrate is thus prevented.Type: ApplicationFiled: March 5, 2002Publication date: April 24, 2003Applicant: Fujitsu LimitedInventors: Takao Ohno, Koichi Meguro, Shigeru Kamada, Keisuke Fukuda, Yuzo Shimobeppu
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Publication number: 20030073264Abstract: A silicon wafer has a first surface having a plurality of semiconductor elements and a second surface opposite to the first surface. The second surface of the silicon wafer is partially removed, by grinding or etching, to form a center portion and a peripheral portion having thickness greater than a thickness of the center portion. The silicon wafer is then separated into the plurality of semiconductor elements.Type: ApplicationFiled: February 6, 2002Publication date: April 17, 2003Applicant: Fujitsu LimitedInventors: Koichi Meguro, Keisuke Fukuda, Yuzo Shimobeppu, Takao Ohno