Abstract: A scrambled video signal processor comprises an amplifier for outputting a noninverted video signal and an inverted video signal, a timing pulse controller for generating first and second timing pulses at a pedestal position in an arbitrary horizontal synchronous signal period of the video signal, and a third timing pulse in an arbitrary video period of the video signal, first and second pedestal clampers for receiving one of the noninverted and inverted video signals from the amplifier and clamping a pedestal level of the arbitrary horizontal synchronous signal period, an offset level controller for receiving the first timing pulse, for DC-restoring to a first level the pedestal position of the horizontal synchronous signal period of the noninverted video signal, and for DC-restoring to a second level, which is different from the first level, the pedestal position of the horizontal synchronous signal period of the inverted signal, a pedestal level controller for DC-restoring to a third level of the other ped

Abstract: A video disc has first and second information tracks adjacently formed thereon, and first and second FM signals with different frequency bands are recorded on the first and second information tracks, respectively. A common stylus simultaneously traces the first and second information tracks, and a signal detector circuit coupled with the stylus detects the first and second FM signals. The first and second FM signals are separated by first and second filter circuits, and applied respectively to first and second rectifying circuits, where DC voltage signals corresponding to the carrier levels of the detected first and second FM signals are produced. These DC voltage signals are compared by a voltage comparator circuit to control a tracking compensating device. Demodulator circuits to demodulate the information signals recorded on the first and second information tracks are connected to the first and second filter circuits.