Patents by Inventor Koichi Miyashita

Koichi Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9223305
    Abstract: A semiconductor manufacturing system includes circuitry configured to execute: displaying a screen for selecting an inspection set including inspection items having a manipulation item and/or a check item; retrieving the inspection items, arranging the inspection items in the order of workflow, and displaying each inspection item on a screen with an execution attribute indicating whether each inspection item is “automatic” or “manual” execution; receiving an inspection start command and reading the first inspection item from a storage unit. The circuitry also executes steps corresponding to the following cases (a) to (d) until there are no more inspection items: (a) the read-out inspection item being the manipulation item and “automatic”; (b) the read-out inspection item being the manipulation item and “manual”; (c) the read-out inspection item being the check item and “automatic”; and (d) the read-out inspection item being the check item and “manual”.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 29, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Gaku Ikeda, Koichi Miyashita, Takamasa Chikuma, Satoshi Gomi, Chunmui Li, Kunio Takano
  • Patent number: 8896111
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanimoto, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuke Dohmae
  • Publication number: 20140070428
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor chip disposed on a circuit board, an adhesive layer fixing the first semiconductor chip to the circuit board, and a second semiconductor chip having an outer shape smaller than that of the first semiconductor chip. At least a part of the second semiconductor chip is embedded in the adhesive layer. The adhesive layer has a thickness in a range of 95 to 150 ?m. The adhesive layer includes a cured product of a thermosetting resin whose thermal time viscosity at a time that the second semiconductor chip is embedded is in a range of 500 to 5000 Pa·s.
    Type: Application
    Filed: March 12, 2013
    Publication date: March 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira TANIMOTO, Takashi Imoto, Yoriyasu Ando, Masashi Noda, Naoki Iwamasa, Koichi Miyashita, Masatoshi Kawato, Masaji Iwamoto, Jun Tanaka, Yusuek Dohmae
  • Patent number: 8581153
    Abstract: A method of detecting an abnormal placement of a substrate W, which is carried out when a substrate W placed on a substrate table 3, in which a heater 6a, 6b is disposed, is processed by heating. The method of detecting an abnormal placement of the substrate comprises the steps of: during processing of the substrate W, based on information about an electric output to the heater 6a, 6b or information about a measured temperature of the substrate table 3, detecting of a maximum value and a minimum value of the electric output or the measured temperature, or an integrated value of the electric output or the measured temperature; and judging of the abnormal placement of the substrate based on the maximum value and the minimum value detected, or the integrated value detected.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: November 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Takashi Chino, Satoshi Gomi, Koichi Miyashita, Minoru Nagasawa, Yoshie Eda
  • Publication number: 20130062758
    Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.
    Type: Application
    Filed: March 16, 2012
    Publication date: March 14, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi IMOTO, Yoriyasu Ando, Akira Tanimoto, Masaji Iwamoto, Yasuo Takemoto, Hideo Taguchi, Naoto Takebe, Koichi Miyashita, Jun Tanaka, Katsuhiro Ishida, Shogo Watanabe, Yuichi Sano
  • Publication number: 20130013240
    Abstract: A semiconductor manufacturing system includes a program for inspecting a device of the system executing: displaying a screen for selecting an inspection set including inspection items having a manipulation item and/or a check item; retrieving the inspection items, arranging the inspection items in the order of workflow, and displaying each inspection item on a screen with an execution attribute indicating whether each inspection item is “automatic” or “manual” execution; receiving an inspection start command and reading the first inspection item from a storage unit. The program also executes steps corresponding to the following cases (a) to (d) until there are no more inspection items: (a) the read-out inspection item being the manipulation item and “automatic”; (b) the read-out inspection item being the manipulation item and “manual”; (c) the read-out inspection item being the check item and “automatic”; and (d) the read-out inspection item being the check item and “manual”.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 10, 2013
    Applicant: TOKYO ELECTON LIMITED
    Inventors: Gaku Ikeda, Koichi Miyashita, Takamasa Chikuma, Satoshi Gomi, Chunmui Li, Kunio Takano
  • Patent number: 8328974
    Abstract: The film sticking apparatus includes: a gripping member; a pressing member pressing the adhesive face of the film being held in a planar state against one end face of a cylindrical honeycomb structure having a plurality of cells, and thus sticking the film to the one end face; and a folding member having an opening portion formed that allows an end of the honeycomb structure on the side to which the film is stuck to be inserted, wherein the folding member folds a protruding portion of the film protruding from the one end face of the honeycomb structure by inserting the honeycomb structure into the opening portion, toward a side face of the honeycomb structure, and simultaneously presses at least a part of the folded protruding portion against a part of the side face of the honeycomb structure to stick the film to the side face.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: December 11, 2012
    Assignee: NGK Insulators, Ltd.
    Inventors: Takeshi Tokunaga, Koichi Miyashita
  • Publication number: 20120248628
    Abstract: According to one embodiment, a semiconductor device includes a control element provided above a main surface of a substrate through a first adhesion layer, a second adhesion layer provided to cover the control element a first semiconductor chip provided on the second adhesion layer, a bottom surface area of the first semiconductor chip being larger than a top surface area of the control element, and at least one side of an outer edge of the control element projecting to an outside of an outer edge of the first semiconductor chip.
    Type: Application
    Filed: September 15, 2011
    Publication date: October 4, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun TANAKA, Koichi Miyashita, Yoriyasu Ando, Akira Tanimoto, Yasuo Takemoto
  • Publication number: 20110174800
    Abstract: A method of detecting an abnormal placement of a substrate W, which is carried out when a substrate W placed on a substrate table 3, in which a heater 6a, 6b is disposed, is processed by heating. The method of detecting an abnormal placement of the substrate comprises the steps of: during processing of the substrate W, based on information about an electric output to the heater 6a, 6b or information about a measured temperature of the substrate table 3, detecting of a maximum value and a minimum value of the electric output or the measured temperature, or an integrated value of the electric output or the measured temperature; and judging of the abnormal placement of the substrate based on the maximum value and the minimum value detected, or the integrated value detected.
    Type: Application
    Filed: September 25, 2009
    Publication date: July 21, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Takashi Chino, Satoshi Gomi, Koichi Miyashita, Minoru Nagasawa, Yoshie Eda
  • Publication number: 20100108242
    Abstract: The film sticking apparatus includes: a gripping member; a pressing member pressing the adhesive face of the film being held in a planar state against one end face of a cylindrical honeycomb structure having a plurality of cells, and thus sticking the film to the one end face; and a folding member having an opening portion formed that allows an end of the honeycomb structure on the side to which the film is stuck to be inserted, wherein the folding member folds a protruding portion of the film protruding from the one end face of the honeycomb structure by inserting the honeycomb structure into the opening portion, toward a side face of the honeycomb structure, and simultaneously presses at least a part of the folded protruding portion against a part of the side face of the honeycomb structure to stick the film to the side face.
    Type: Application
    Filed: October 5, 2009
    Publication date: May 6, 2010
    Applicant: NGK INSULATORS, LTD.
    Inventors: Takeshi TOKUNAGA, Koichi MIYASHITA
  • Publication number: 20070214964
    Abstract: There is disclosed a method for removing bubbles from a slurry and a device therefor capable of efficiently optimizing the removal of bubbles from a slurry and the viscosity of the slurry as well as dramatically reducing the bubble removing time.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 20, 2007
    Applicant: NGK INSULATORS, LTD.
    Inventors: Koichi Miyashita, Yukihito Ichikawa
  • Publication number: 20070212483
    Abstract: Problem to be solved is to provide a means to make the thickness of a ceramic slurry in a container uniformly in a process to form plugged portions in a honeycomb structure. The solution is provided with a slurry applying device 1 comprising a plate shaped container 2 which a base 21 is flat, a fixed quantity non-pulsatile pump 3 to which a slurry 31 is discharged to the base 21 of the container 2, a discharge opening moving means which relatively moves a position of a discharge opening of the pump 3 between center 22 and periphery 23 of the base 21 of the container 2, and a container rotating means for application which rotates the container 2 as a rotating axis with the center 22 of the base 21.
    Type: Application
    Filed: February 21, 2007
    Publication date: September 13, 2007
    Applicant: NGK INSULATORS, LTD.
    Inventors: Koichi Miyashita, Yukihito Ichikawa
  • Publication number: 20060174695
    Abstract: A method and a device for inspecting a honeycomb structure having porous partition walls (2) disposed so as to form a plurality of flow passages (3a) and (3b) passed through the honeycomb structure from one end face (42) to the other end face (44), the device comprising a water particle generating part (11) generating water particles (10), a water particle lead-in part (12) leading the water particles (10) into the plurality of flow passages (3a), and a discharged particle measuring part (13) measuring the particle size distribution and the quantity of particles of the water particles (10) discharged from the plurality of flow passages (3b). By the device and method, the honeycomb structure can be easily inspected for presence or absence of defects, sizes of defects, quantity of defects, and the sizes and quantity of pits, and a post-treatment can also be easily performed.
    Type: Application
    Filed: March 4, 2004
    Publication date: August 10, 2006
    Applicant: NGK Insulators, Ltd.
    Inventors: Koichi Miyashita, Shinya Mori
  • Publication number: 20050169033
    Abstract: A high speed operating circuit such as a data processor chip and memory chips constituting an electronic circuit is mounted to a multilayer wiring substrate in the state of a bare chip, and is set to a multichip module. This multichip module is mounted to a wiring substrate constituting the electronic circuit. In the multichip module, buffer circuits are inserted into a module internal bus commonly connected to the data processor chip and the memory chips. The buffer circuits are set to an address output buffer, a control signal output buffer and a data input/output buffer set to a high impedance state in accordance with an operating selection of the memory chips. When high frequency noise resisting characteristics are strengthened by the multilayer wiring substrate and the data processor chip gets access to the memory chips, an external noise tends to flow into a memory through the module internal bus connected to the data processor chip and the memory chips.
    Type: Application
    Filed: April 1, 2005
    Publication date: August 4, 2005
    Inventors: Norihiko Sugita, Takafumi Kikuchi, Koichi Miyashita, Hikaru Ikegami
  • Patent number: 6626717
    Abstract: In a manufacturing step for forming an organic EL element, the organic EL element is provided so as to have an anode and a cathode with a luminescent layer having an organic luminescent material interposed therebetween. Then, an aging treatment is performed. In the aging treatment, a curve of change in luminance with time is measured in driving the organic EL element at constant current. Then, the curve of change in luminance with time is divided into a component having a slowest luminance age-deterioration rate and other components by analyzing the curve and forming a fitting curve having a plurality of members that is fitted to the curve of change in luminance with time. Moreover, the aging treatment is conducted until a luminance of the element becomes approximately equal to an initial value A1 of the component having a slowest luminance age-deterioration rate.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: September 30, 2003
    Assignee: Denso Corporation
    Inventors: Koichi Miyashita, Takayoshi Kuriyama, Masahiko Ishii
  • Publication number: 20020123291
    Abstract: In a manufacturing step for forming an organic EL element, the organic EL element is provided so as to have an anode and a cathode with a luminescent layer having an organic luminescent material interposed therebetween. Then, an aging treatment is performed. In the aging treatment, a curve of change in luminance with time is measured in driving the organic EL element at constant current. Then, the curve of change in luminance with time is divided into a component having a slowest luminance age-deterioration rate and other components by analyzing the curve and forming a fitting curve having a plurality of members that is fitted to the curve of change in luminance with time. Moreover, the aging treatment is conducted until a luminance of the element becomes approximately equal to an initial value A1 of the component having a slowest luminance age-deterioration rate.
    Type: Application
    Filed: December 21, 2001
    Publication date: September 5, 2002
    Inventors: Koichi Miyashita, Takayoshi Kuriyama, Masahiko Ishii
  • Patent number: 6392293
    Abstract: Outer leads extend outward from within a package that seals a semiconductor chip, and they are connected to the semiconductor chip inside the package. Depressions are formed at the distal end portions of the outer leads. The depressions are coated with a material which is one of: Sn—Pb, Sn—Ag, Sn—Bi, Sn—Zn, Sn—Cu, Pd, Au and Ag. The depressions are V-shaped, U-shaped, or rectangular. Each depression has a depth which is 30% to 75% with respect to the thickness which the outer lead has at the cut end face of distal end thereof. The outer leads are either a gull-wing type or a straight type.
    Type: Grant
    Filed: June 3, 1999
    Date of Patent: May 21, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Sugihara, Koichi Miyashita
  • Patent number: 6337730
    Abstract: According to this liquid crystal cell, a vacuum to be established between two electrode substrates as a result of the volume shrinkage of a liquid crystal having a high viscosity at the room temperature can be damped by communicating between two of a plurality of filling portions formed between two electrode substrates by a plurality of barrier walls through the intervening barrier walls. An anti-ferroelectric liquid crystal (AFLC) is used as the liquid crystal. The liquid crystal cell has a lower electrode substrate and an upper electrode substrate, between which a smectic liquid crystal is disposed together with a plurality of barrier walls on the inner side of a band seal. Each barrier wall has through holes to communicate between the two filling portions located on the two sides of the barrier walls.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: January 8, 2002
    Assignee: Denso Corporation
    Inventors: Masaaki Ozaki, Koichi Miyashita, Kenji Maekawa, Takahisa Kaneko, Naoki Matsumoto, Kazuhiro Inoguchi
  • Publication number: 20010052643
    Abstract: Outer leads extend outward from within a package that seals a semiconductor chip, and they are connected to the semiconductor chip inside the package. Depressions are formed at the distal end portions of the outer leads. The depressions are coated with a material which is one of: Sn—Pb, Sn—Ag, Sn—Bi, Sn—Zn, Sn—Cu, Pd, Au and Ag. The depressions are V-shaped, U-shaped, or rectangular. Each depression has a depth which is 30% to 75% with respect to the thickness which the outer lead has at the cut end face of distal end thereof. The outer leads are either a gull-wing type or a straight type.
    Type: Application
    Filed: June 3, 1999
    Publication date: December 20, 2001
    Inventors: KOICHI SUGIHARA, KOICHI MIYASHITA
  • Publication number: 20010044774
    Abstract: An economical data processing system, including: a means to form a virtual space in use with a network which includes a plurality of computers connected to each other; a means to form virtual currency which represents a value index in the virtual space; and a virtual currency storing means to store the virtual currency. In the economical data processing system, the virtual currency is delivered in the virtual space.
    Type: Application
    Filed: April 25, 2001
    Publication date: November 22, 2001
    Inventors: Tatsuya Sasazawa, Masatoshi Tachibana, Takashi Saita, Koichi Miyashita