Abstract: Provided are a flame retardant composition for expandable styrene resin that can be used to produce a foamed molded article having excellent flame retardancy and excellent heat resistance, a flame-retardant expandable styrene-based resin composition, and an extrusion-foamed molded article of the styrene-based resin compostion. The flame retardant composition for expandable styrene resin of the present invention comprises at least tetrabromobisphenol A-bis(2,3-dibromo-2-methylpropyl ether) as a component (B1), fatty acid zinc as a component (C), and a fatty acid metal salt, excluding the component (C), as a component (D), the component (C) being contained in an amount of 0.1 to 15 parts by mass based on 100 parts by mass of the component (B1), and the component (D) being contained in an amount of 1 to 35 parts by mass based on 100 parts by mass of the component (B1).

Abstract: An object of the present invention is to provide a method of assisting diagnosis of inflammatory bowel disease, which can specifically determine inflammatory bowel disease. The present invention relates to “a method of assisting diagnosis of inflammatory bowel disease, the method including subjecting a subject-derived specimen to a reduction treatment and subsequently measuring a human prohaptoglobin amount in the specimen by using an antibody 1 which is an antibody that specifically binds to an amino acid sequence set forth in SEQ ID NO: 1, and determining that a subject has inflammatory bowel disease by using the human prohaptoglobin amount as an indicator, and relates to an examination kit for assisting diagnosis of inflammatory bowel disease, including the antibody 1 a reducing agent”.

Abstract: There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

Abstract: There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.

Abstract: A bus system comprises a plurality of bus modules each for performing data transfer between a master module and a slave module. A power control module controls transition to a power-saving mode of each bus module based on communication with the plurality of bus modules. The power control module comprises a plurality of control modules corresponding to the plurality of bus modules respectively. Each control module performs communication with the corresponding bus module using power control signals.

Abstract: If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration. When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.

Abstract: A bus system comprises a plurality of bus modules each for performing data transfer between a master module and a slave module. A power control module controls transition to a power-saving mode of each bus module based on communication with the plurality of bus modules. The power control module comprises a plurality of control modules corresponding to the plurality of bus modules respectively. Each control module performs communication with the corresponding bus module using power control signals.

Abstract: According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data.

Abstract: If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing. Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.

Abstract: An image forming apparatus which forms a halftone image on a print medium (200) using multipass processing of scanning a single area on the print medium (200) by a printhead (220) N times and forming dots every scan operation includes a pass division table (410) used to set the print density ratio of each scan operation, a print data generation unit (370) which generates print data of each scan operation, a printer engine (180) which prints a halftone image on the print medium (200) on the basis of the generated print data, and a sensor (340) which detects the state of printing on the print medium (200) by the printer engine (180). The print data generation unit (370) corrects print data in synchronism with printing by the printer engine (180) on the basis of the set print density ratio and the detected printing state.

Abstract: If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information processing apparatus may require an additional process for adjusting a data latch timing. Delay information indicating a relationship between a calibration pattern to be received and an amount of cycle delay is stored in advance. Thus, the time required for detecting an amount of cycle delay, which is equivalent to the amount by which a signal for controlling a data latch mechanism in the information processing apparatus to stop its operation is delayed, can be reduced.

Abstract: If data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller, a delay may not necessarily be detected with an existing configuration. When a data latch timing of the external device controller is adjusted, gating of or releasing gating of an output clock of the external device controller is performed in accordance with predetermined gating information, thus improving the accuracy of calibration for adjusting the data latch timing.

Abstract: An image forming apparatus which forms a halftone image on a print medium (200) using multipass processing of scanning a single area on the print medium (200) by a printhead (220) N times and forming dots every scan operation includes a pass division table (410) used to set the print density ratio of each scan operation, a print data generation unit (370) which generates print data of each scan operation, a printer engine (180) which prints a halftone image on the print medium (200) on the basis of the generated print data, and a sensor (340) which detects the state of printing on the print medium (200) by the printer engine (180). The print data generation unit (370) corrects print data in synchronism with printing by the printer engine (180) on the basis of the set print density ratio and the detected printing state.

Abstract: An image forming apparatus which forms a halftone image on a print medium (200) using multipass processing of scanning a single area on the print medium (200) by a printhead (220) N times and forming dots every scan operation includes a pass division table (410) used to set the print density ratio of each scan operation, a print data generation unit (370) which generates print data of each scan operation, a printer engine (180) which prints a halftone image on the print medium (200) on the basis of the generated print data, and a sensor (340) which detects the state of printing on the print medium (200) by the printer engine (180). The print data generation unit (370) corrects print data in synchronism with printing by the printer engine (180) on the basis of the set print density ratio and the detected printing state.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: According to the present invention, a phase shift of data received by an external device controller is delayed and corrected, and a control signal used for the data load control on the external device controller side is delayed period-by-period. Further, the phase shift is adjusted and then the control signal is adjusted. The adjustment can beneficially be performed very quickly. Moreover, the present invention is also beneficial for preventing a failure to load data.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A search processor for performing search processes by comparing data registered in a database with a search key includes a search database in which data to be searched for is registered and that outputs the registered data according to an input address. The processor further includes a search segment database in which address segment information and bit segment information are registered. It outputs the registered information, the address segment information indicating address segmentation in the search database and the bit segment information indicating bit-position segmentation in the search database. A search address used in the search database is generated based on the address segment information. The bit position of data registered at that search address is then converted based on the bit segment information, and the converted data is compared with the search key so as to output comparison results.

Abstract: To provide an image processing technique compatible with both a CCD and a CIS, which controls storage of image data read by each device in a memory and the read of the stored data for each rectangular area to obtain a high memory efficiency, an image processing apparatus includes an input section which executes input processing of image data read by an image reading device in accordance with the data output format of the device, an output data control section which distributes the image data that has undergone the input processing by the input section in accordance with the output format of the image reading device, an address generation section which generates address information corresponding to the output format to store the distributed image data in a memory, and a memory control section which DMA-transfers the distributed image data to the memory and stores the image data on the basis of the generated address information.