Abstract: An electrode body housed, in a cylindrical battery can, in a spirally wound arrangement includes a sheet-like positive electrode, a sheet-like negative electrode, and a first separator laminate and a second separator laminate with one of the positive and negative electrodes therebetween (the negative electrode in the example of FIG. 2). Each of the first separator laminate and the second separator laminate has a layered structure including two or more separators (two in FIG. 2) welded together by a first weld region extending in a longitudinal direction along a first side and a second weld region extending in the longitudinal direction along a second side opposing the first side. The first separator laminate and the second separator laminate are welded together by a third weld region extending in the longitudinal direction along the first side and a fourth weld region extending in the longitudinal direction along the second side.

Abstract: A semiconductor integrated circuit capable of decreasing the amount of signal transmission when an FET is in an OFF state and of improving a variable ratio of the amount of signal transmission, including an inductor element provided between the source terminal and ground terminal of an FET; and Lo input matching circuit provided between the gate terminal and input terminal of the FET; a bias supply circuit connected to the gate terminal of the FET; an RF output matching circuit provided between the drain terminal and output terminal of the FET; a control signal input circuit connected to the drain terminal of the FET; and a bias supply circuit connected to the source terminal of the FET. Since the reactance component of the gate-to-source impedance of the FET series-resonates with the inductor element 1 when the FET is in the OFF state, the amount of signal transmission can be sufficiently small when the FET is in the OFF state, and the variable ratio of the amount of signal transmission can be improved.

Abstract: It is an object of the present invention to provide a semiconductor integrated circuit capable of decreasing the amount of signal transmission when an FET is in an OFF state and of improving a variable ratio of the amount of signal transmission.

Abstract: In a sampling signal generation circuit, means for producing a plurality of clock signals from a reference clock signal is provided. The transition points of these clock signals are compared with those of a signal to be sampled. As the result of this comparison, the most suitable clock signal is selected to be a sampling signal, in order to carry out a sampling of the signal.

Abstract: In a high-speed signal multiplexing circuit, when data supplied to an input terminal of a flip-flop circuit differs from the data which has been latched in the flip-flop circuit, an exclusive OR circuit supplies a control signal to a clock signal input terminal of the flip-flop circuit. The flip-flop circuit latches the data supplies to the input terminal in response to the control signal. A data reading section generates a read signal in synchronism with a clock signal. The data latched in the flip-flop circuit is successively read out in response to the read signal.