Patents by Inventor Koichi Murakami

Koichi Murakami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12047796
    Abstract: A wireless communication system includes a plurality of wireless base stations and a measurement station, each wireless base station including a wireless communication unit, a wireless information collection unit, and a measurement result collection unit, the measurement station being configured to control the plurality of wireless base stations, wherein the measurement station generates a measurement condition based on wireless environment information collected by the wireless information collection unit of each wireless base station and notifies each wireless base station of a measurement control signal corresponding to the measurement condition, each wireless base station sends traffic addressed to a subordinate wireless terminal station or broadcast traffic at the same time in accordance with the notified measurement control signal, a measurement result collection unit of a wireless base station that is a measurement target measures wireless communication performance and notifies the measurement station o
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 23, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Toshiro Nakahira, Tomoki Murakami, Hirantha Abeysekera, Koichi Ishihara, Takafumi Hayashi, Yasushi Takatori
  • Publication number: 20230420453
    Abstract: A semiconductor device includes a semiconductor substrate and a lower electrode. The semiconductor substrate includes a collector region of p-type and a cathode region of n-type being in contact with the lower electrode. The semiconductor substrate has an insulated gate bipolar transistor range overlapping with the collector region when viewed along a thickness direction of the semiconductor substrate, and a diode range overlapping with the cathode region when viewed along the thickness direction of the semiconductor substrate. The semiconductor substrate further includes a buffer region of n-type being in contact with upper surfaces of the collector region and the cathode region, a drift region of n-type being in contact with an upper surface of the buffer region, and a current limiting region of p-type disposed above a boundary between the collector region and the cathode region and being in contact with an upper surface of the buffer region.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventor: Koichi MURAKAMI
  • Patent number: 11843048
    Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: December 12, 2023
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
  • Publication number: 20230367230
    Abstract: An exposure apparatus includes: light source that emits exposure light; exposure pattern forming apparatus including a plurality of exposure elements and disposed on an optical path of at least part of exposure light; and control unit electrically connected to exposure pattern forming apparatus, in which control unit controls whether workpiece is irradiated with exposure light via each of exposure elements by switching each of exposure elements to a first or second state, and integrates exposure amount in predetermined region of scheduled exposure region by sequentially irradiating predetermined region with light of part of exposure light via a first exposure element in first state among plurality of exposure elements and light of part of exposure light via second exposure element in the first state different from the first exposure element among the plurality of exposure elements in accordance with a relative movement of the workpiece and the exposure pattern forming apparatus.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Applicant: NIKON CORPORATION
    Inventors: Koichi MURAKAMI, Koutarou TAKIGAMI, Tetsuya ABE
  • Publication number: 20230288238
    Abstract: The sensor of a fluid sensor system includes an outer peripheral sensor unit including three or more sensor pairs to surround and sandwich the heating element. The computing device of the system includes a first identification unit identifies a sensor pair in which an output difference between an output value corresponding to a temperature detected by one temperature sensor of the sensor pair and an output value corresponding to a temperature detected by the other temperature sensor of the sensor pair is largest, a second identification unit identifies other sensor pairs adjacent to the identified sensor pair in the circumferential direction, and a flow direction estimation unit estimates the flow direction of the fluid on the basis of the output difference in the sensor pair having the largest output difference and output differences in the other sensor pairs adjacent to the sensor pair in the circumferential direction.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 14, 2023
    Applicants: MITSUBISHI HEAVY INDUSTRIES, LTD., Tokyo University of Science Foundation
    Inventors: Shunsuke MIZUMI, Naoto OMURA, Masahiro MOTOSUKE, Daiki SHIRAISHI, Koichi MURAKAMI
  • Patent number: 11548827
    Abstract: Provided is a member for a plasma processing apparatus consisting of a tungsten carbide phase. The member includes at least one type of atom selected from the group consisting of a Fe atom, a Co atom, and a Ni atom, in which the total content of the atoms is in a range of 30 to 3300 atomic ppm.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: January 10, 2023
    Assignees: NIPPON TUNGSTEN CO., LTD., TOKYO ELECTRON LIMITED
    Inventors: Takashi Ikeda, Hajime Ishii, Kenji Fujimoto, Naoyuki Satoh, Nobuyuki Nagayama, Koichi Murakami, Takahiro Murakami
  • Patent number: 11434174
    Abstract: A member for a plasma processing apparatus has a tungsten carbide phase, and a sub-phase including at least one selected from the group consisting of phase I to IV, and phase V, in which the phase I is a carbide phase containing, as a constituent element, at least one of the elements of Group IV, V, and VI of the periodic table excluding W, the phase II is a nitride phase containing, as a constituent element, at least one of the elements of Group IV, V, and VI of the periodic table excluding W, the phase III is a carbonitride phase containing, as a constituent element, at least one of the elements of Group IV, Group V, and Group VI of the periodic table excluding W, the phase IV is a carbon phase, the phase V is a composite carbide phase which is represented by a formula WxMyCz.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 6, 2022
    Assignees: NIPPON TUNGSTEN CO., LTD., TOKYO ELECTRON LIMITED
    Inventors: Takashi Ikeda, Hajime Ishii, Kenji Fujimoto, Naoyuki Satoh, Nobuyuki Nagayama, Koichi Murakami, Takahiro Murakami
  • Publication number: 20220246755
    Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi MURAKAMI
  • Patent number: 11404251
    Abstract: A cooling table includes a first portion, a second portion, a first path, a second path and a third path. An electrostatic chuck is provided on the first portion, and the first portion is provided on the second portion. The first path is provided within the first portion, and the second path is provided within the second portion. The third path is connected to the first path and the second path. A chiller unit is connected to the first path and the second path. The first path is extended within the first portion along the electrostatic chuck, and the second path is extended within the second portion along the electrostatic chuck. A coolant outputted from the chiller unit passes through the first path, the third path and the second path in sequence, and then is inputted to the chiller unit.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 2, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shin Yamaguchi, Akiyoshi Mitsumori, Takehiko Arita, Koichi Murakami
  • Patent number: 11342452
    Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 24, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
  • Patent number: 10818496
    Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 27, 2020
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
  • Publication number: 20200317582
    Abstract: A member for a plasma processing apparatus has a tungsten carbide phase, and a sub-phase including at least one selected from the group consisting of phase I to IV, and phase V, in which the phase I is a carbide phase containing, as a constituent element, at least one of the elements of Group IV, V, and VI of the periodic table excluding W, the phase II is a nitride phase containing, as a constituent element, at least one of the elements of Group IV, V, and VI of the periodic table excluding W, the phase III is a carbonitride phase containing, as a constituent element, at least one of the elements of Group IV, Group V, and Group VI of the periodic table excluding W, the phase IV is a carbon phase, the phase V is a composite carbide phase which is represented by a formula WxMyCz.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 8, 2020
    Inventors: Takashi IKEDA, Hajime ISHII, Kenji FUJIMOTO, Naoyuki SATOH, Nobuyuki NAGAYAMA, Koichi MURAKAMI, Takahiro MURAKAMI
  • Publication number: 20200317583
    Abstract: Provided is a member for a plasma processing apparatus consisting of a tungsten carbide phase. The member includes at least one type of atom selected from the group consisting of a Fe atom, a Co atom, and a Ni atom, in which the total content of the atoms is in a range of 30 to 3300 atomic ppm.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 8, 2020
    Inventors: Takashi IKEDA, Hajime ISHII, Kenji FUJIMOTO, Naoyuki SATOH, Nobuyuki NAGAYAMA, Koichi MURAKAMI, Takahiro MURAKAMI
  • Patent number: 10659636
    Abstract: Provided is an image forming apparatus including a charge processing section and an operation section that are brought closer in height to each other, thus improving the operability of a user. The image forming apparatus (100) includes a coin insertion processing section (110), an operation panel (120) and an electrophotography printer (130). The coin insertion processing section (110) is configured to accept money and then execute charge processing so as to permit image formation by the image forming apparatus (100). The operation panel (120) is configured to, when the coin insertion processing section (110) executes the charge processing, accept setting of image formation by the image forming apparatus (100). The electrophotography printer (130) is configured to form an image of the read image data based on setting at the operation panel (120). The coin insertion processing section (110) is disposed at a height equal to a height of the operation panel (120).
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: May 19, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Koichi Murakami
  • Publication number: 20200119187
    Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.
    Type: Application
    Filed: December 27, 2017
    Publication date: April 16, 2020
    Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi MURAKAMI
  • Publication number: 20200020536
    Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.
    Type: Application
    Filed: July 26, 2019
    Publication date: January 16, 2020
    Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi Murakami
  • Publication number: 20190260895
    Abstract: Provided is an image forming apparatus including a charge processing section and an operation section that are brought closer in height to each other, thus improving the operability of a user. The image forming apparatus (100) includes a coin insertion processing section (110), an operation panel (120) and an electrophotography printer (130). The coin insertion processing section (110) is configured to accept money and then execute charge processing so as to permit image formation by the image forming apparatus (100). The operation panel (120) is configured to, when the coin insertion processing section (110) executes the charge processing, accept setting of image formation by the image forming apparatus (100). The electrophotography printer (130) is configured to form an image of the read image data based on setting at the operation panel (120). The coin insertion processing section (110) is disposed at a height equal to a height of the operation panel (120).
    Type: Application
    Filed: May 6, 2019
    Publication date: August 22, 2019
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Koichi MURAKAMI
  • Patent number: 10326900
    Abstract: Provided is an image forming apparatus including a charge processing section and an operation section that are brought closer in height to each other, thus improving the operability of a user. An image forming apparatus (100) includes a coin insertion processing section (110), an operation panel (120) and an electrophotography printer (130). The coin insertion processing section (110) is configured to accept money and then execute charge processing so as to permit image formation by the image forming apparatus (100). The operation panel (120) is configured to, when the coin insertion processing section (110) executes the charge processing, accept setting of image formation by the image forming apparatus (100). The electrophotography printer (130) is configured to form an image of the read image data based on setting at the operation panel (120). The coin insertion processing section (110) is disposed at a height equal to a height of the operation panel (120).
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: June 18, 2019
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Koichi Murakami
  • Publication number: 20180218886
    Abstract: A cooling table includes a first portion, a second portion, a first path, a second path and a third path. An electrostatic chuck is provided on the first portion, and the first portion is provided on the second portion. The first path is provided within the first portion, and the second path is provided within the second portion. The third path is connected to the first path and the second path. A chiller unit is connected to the first path and the second path. The first path is extended within the first portion along the electrostatic chuck, and the second path is extended within the second portion along the electrostatic chuck. A coolant outputted from the chiller unit passes through the first path, the third path and the second path in sequence, and then is inputted to the chiller unit.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 2, 2018
    Inventors: Shin Yamaguchi, Akiyoshi Mitsumori, Takehiko Arita, Koichi Murakami
  • Publication number: 20170069470
    Abstract: An upper electrode structure includes a first plate, a second plate and an electrostatic attraction unit. The first plate has a first region, a second region and a third region which are concentrically arranged. Each of the regions is provided with a multiple number of gas discharge openings. The electrostatic attraction unit is provided between the first plate and the second plate and is configured to attract the first plate. The electrostatic attraction unit is equipped with a first to third heaters for the first to third regions. The electrostatic attraction unit and the second plate provide a first supply path, a second supply path and a third supply path through which gases are supplied into the first to third regions, respectively. A first gas diffusion space, a second gas diffusion space and a third gas diffusion space are formed in the electrostatic attraction unit.
    Type: Application
    Filed: April 28, 2015
    Publication date: March 9, 2017
    Inventors: Koichi Murakami, Michishige Saito, Keita Kambara, Kenji Nagai