Patents by Inventor Koichi Muraoka
Koichi Muraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10553729Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: August 29, 2018Date of Patent: February 4, 2020Assignee: Toshiba Memory CorporationInventors: Takamitsu Ishihara, Koichi Muraoka
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Publication number: 20190027609Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is forced on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: ApplicationFiled: August 29, 2018Publication date: January 24, 2019Applicant: Toshiba Memory CorporationInventors: Takamitsu ISHIHARA, Koichi Muraoka
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Patent number: 10074749Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: April 11, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takamitsu Ishihara, Koichi Muraoka
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Patent number: 9620653Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: December 16, 2015Date of Patent: April 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 9448191Abstract: An X-ray fluorescence spectrometer irradiates a measurement sample 1 with primary X rays from an X-ray source, and excites an element in the sample 1 to emit fluorescence X rays, and the primary X-rays are partially scattered as scattered X rays from the sample 1. A spectroscopic system is placed so that a first spectroscopic unit, a second spectroscopic unit, and a single X-ray detector form an optimized optical system. The first spectroscopic unit disperses the fluorescence X rays to collect the resultant X rays onto the X-ray detector. The second spectroscopic unit disperses the scattered X rays to collect the resultant X rays onto the X-ray detector. In this manner, the spectroscopic system disperses the fluorescence X rays and the scattered X rays so that the intensity of the fluorescence X rays and the intensity of the scattered X rays can be detected by the single X-ray detector 24.Type: GrantFiled: December 21, 2012Date of Patent: September 20, 2016Assignee: Techno-X Co., Ltd.Inventors: Tadashi Utaka, Koichi Muraoka
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Publication number: 20160225910Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: ApplicationFiled: April 11, 2016Publication date: August 4, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takamitsu ISHIHARA, Koichi MURAOKA
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Patent number: 9379320Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.Type: GrantFiled: January 31, 2012Date of Patent: June 28, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka
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Patent number: 9331167Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: June 24, 2014Date of Patent: May 3, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takamitsu Ishihara, Koichi Muraoka
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Publication number: 20160104802Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: December 16, 2015Publication date: April 14, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Patent number: 9252290Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: March 16, 2015Date of Patent: February 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 9246014Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: March 16, 2015Date of Patent: January 26, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20150194520Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: March 16, 2015Publication date: July 9, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Publication number: 20150187792Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: ApplicationFiled: March 16, 2015Publication date: July 2, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masao SHINGU, Jun FUJIKI, Naoki YASUDA, Koichi MURAOKA
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Patent number: 9012978Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: August 30, 2013Date of Patent: April 21, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Patent number: 8987809Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory element including: a semiconductor substrate including: a source region; a drain region; and a channel region; a lower insulating film that is formed on the channel region; a charge storage film that is formed on the lower insulating film and that stores data; an upper insulating film that is formed on the charge storage film; and a control gate that is formed on the upper insulating film, wherein the upper insulating film includes: a first insulting film; and a second insulating film that is laminated with the first insulating film, and wherein the first insulating film is formed to have a trap level density larger than that of the second insulating film.Type: GrantFiled: August 30, 2013Date of Patent: March 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Jun Fujiki, Naoki Yasuda, Koichi Muraoka
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Publication number: 20140306281Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: ApplicationFiled: June 24, 2014Publication date: October 16, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takamitsu ISHIHARA, Koichi Muraoka
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Patent number: 8796753Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: January 2, 2014Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takamitsu Ishihara, Koichi Muraoka
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Patent number: 8779502Abstract: According to one embodiment, a nonvolatile semiconductor memory includes first to n-th (n is a natural number not less than 2) semiconductor layers in a first direction and extend in a second direction, and the semiconductor layers having a stair case pattern in a first end of the second direction, a common semiconductor layer connected to the first to n-th semiconductor layers commonly in the first end of the second direction, first to n-th layer select transistors which are provided in order from the first electrode side between the first electrode and the first to n-th memory strings, and first to n-th impurity regions which make the i-th layer select transistor (i is one of 1 to n) a normally-on state in the first end of the second direction of the i-th semiconductor layer.Type: GrantFiled: December 12, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Atsuhiro Kinoshita, Masahiro Kiyotoshi, Daisuke Hagishima, Koichi Muraoka
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Patent number: 8759896Abstract: There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material.Type: GrantFiled: October 31, 2012Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Koichi Muraoka
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Patent number: 8754467Abstract: A semiconductor device includes: a semiconductor region; a plurality of stacked structures each of which is disposed on the semiconductor region and has a tunnel insulating film, a charge storage layer, an upper insulating layer, and a control electrode stacked sequentially; an element isolation insulating layer disposed on side faces of the plurality of stacked structures; and a source-drain region disposed on the semiconductor region and among the plurality of stacked structures. The element isolation insulating layer includes at least one of SiO2, SiN, and SiON, the upper insulating layer is an oxide containing at least one metal M selected from the group consisting of a rare earth metal, Y, Zr, and Hf, and Si, and respective lengths Lcharge, Ltop, and Lgate of the charge storage layer, the upper insulating layer, and the control electrode in a channel length direction satisfy the relation “Lcharge<Ltop and Lgate<Ltop”.Type: GrantFiled: July 18, 2013Date of Patent: June 17, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masao Shingu, Akira Takashima, Koichi Muraoka