Patents by Inventor Koichi Naniwae

Koichi Naniwae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130126907
    Abstract: [Problem] To provide a group III nitride semiconductor device and a method for manufacturing the same in which dislocation density in a semiconductor layer can be precisely reduced. [Solution] In manufacturing a group III nitride semiconductor device 1, a mask layer 40 is formed on a substrate 20, followed by selectively growing nanocolumns 50 made of a group III nitride semiconductor through a pattern 44 of the mask layer 40 in order to grow a group III nitride semiconductor layer 10 on the mask layer 40.
    Type: Application
    Filed: November 25, 2011
    Publication date: May 23, 2013
    Applicant: EL-SEED Corporation
    Inventors: Tsukasa Kitano, Koichi Naniwae, Masayoshi Koike, Fumiharu Teramae, Toshiyuki Kondo, Atsushi Suzuki, Tomohiko Maeda, Midori Mori
  • Publication number: 20100252914
    Abstract: In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate.
    Type: Application
    Filed: June 21, 2010
    Publication date: October 7, 2010
    Applicant: NEC CORPORATION
    Inventor: Koichi NANIWAE
  • Publication number: 20090257467
    Abstract: A laser diode 300 includes a p-type GaN guide layer 107, a current confinement layer 314 provided on the p-type GaN guide layer 107 and having an opening 314A formed therein, and a p-type cladding layer 108 provided on the current confinement layer 314 and plugging the opening 314A formed in the current confinement layer 314. An interface between the p-type cladding layer 108 and the p-type GaN guide layer 107 is located in a bottom of the opening 314A. The current confinement layer 314 is a layer of a group III nitride semiconductor, and a width dimension of the opening 314A is minimized in the upper side of the opening 314A.
    Type: Application
    Filed: December 5, 2006
    Publication date: October 15, 2009
    Inventors: Koichi Naniwae, Ichiro Masumoto
  • Patent number: 7454111
    Abstract: Input ports (103a, 103b) formed from fundamental mode waveguides are provided at one end of a multimode waveguide (104). Further, an output port (105) formed from a fundamental mode waveguide is provided at the other end of the multimode waveguide (104). The multimode waveguide (104) has a width wider than those of the input ports (103a, 103b) and the output port (105), and provides modes including multimode to the waveguide. The multimode waveguide (104) is embedded with a buried layer (200). Both of the end faces of the multimode waveguide (104) are made to be planes equivalent to a (100) plane or planes inclined from these planes. In a case of inclined planes, the planes are made to be planes inclined to a direction that the waveguide region spreads toward a stacked direction of the semiconductor layers.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: November 18, 2008
    Assignee: NEC Corporation
    Inventors: Kazuhiro Shiba, Koichi Naniwae, Shinya Sudo, Koji Kudo
  • Publication number: 20070020933
    Abstract: In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate.
    Type: Application
    Filed: September 24, 2003
    Publication date: January 25, 2007
    Inventor: Koichi Naniwae
  • Publication number: 20070003183
    Abstract: Input ports (103a, 103b) formed from fundamental mode waveguides are provided at one end of a multimode waveguide (104). Further, an output port (105) formed from a fundamental mode waveguide is provided at the other end of the multimode waveguide (104). The multimode waveguide (104) has a width wider than those of the input ports (103a, 103b) and the output port (105), and provides modes including multimode to the waveguide. The multimode waveguide (104) is embedded with a buried layer (200). Both of the end faces of the multimode waveguide (104) are made to be planes equivalent to a (100) plane or planes inclined from these planes. In a case of inclined planes, the planes are made to be planes inclined to a direction that the waveguide region spreads toward a stacked direction of the semiconductor layers.
    Type: Application
    Filed: August 30, 2004
    Publication date: January 4, 2007
    Applicant: NEC Corporation
    Inventors: Kazuhiro Shiba, Koichi Naniwae, Shinya Sudo, Koji Kudo
  • Patent number: 6681064
    Abstract: All of a plurality of visible semiconductor light emitting devices, optical waveguides coupled to these visible semiconductor light emitting devices, and a mutiplexer for multiplexing lights from the optical waveguides to prepare multi-wavelength or white light are integrally provided on a single substrate. By virtue of the above construction, a multi-wavelength semiconductor light source can be realized which can reduce the trouble of regulating the optical axis of the optical waveguides and the multiplexer and can contribute to a reduction in cost and a reduction in size.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: January 20, 2004
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Publication number: 20020159705
    Abstract: All of a plurality of visible semiconductor light emitting devices, optical waveguides coupled to these visible semiconductor light emitting devices, and a mutiplexer for multiplexing lights from the optical waveguides to prepare multi-wavelength or white light are integrally provided on a single substrate. By virtue of the above construction, a multi-wavelength semiconductor light source can be realized which can reduce the trouble of regulating the optical axis of the optical waveguides and the multiplexer and can contribute to a reduction in cost and a reduction in size.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 31, 2002
    Applicant: NEC CORPORATION
    Inventor: Koichi Naniwae
  • Patent number: 6320208
    Abstract: A layer structure for a II-VI compound semiconductor device is formed on a GaAs substrate of III-V compound, wherein lattice mismatching is prevented by a first layer interposed between the GaAs substrate and a II-VI compound semiconductor active layer and made of III-V compound semiconductor including In element as a constituent element thereof. The thickness of the first layer is less than the critical thickness allowing coherent growth. Alternatively, the III-V compound of the first layer has a lattice constant substantially equal to the lattice constant of the GaAs substrate. The first layer may be a superlattice layer.
    Type: Grant
    Filed: March 8, 1999
    Date of Patent: November 20, 2001
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Patent number: 6178190
    Abstract: A semiconductor light emitting device has a stacked structure including an n-type clad layer, an active layer, and a p-type clad layer on an InP substrate. The p-type clad layer is made from an MgZnSeTe-based compound semiconductor lattice-matched with InP. The n-type clad layer is made from a compound semiconductor lattice-matched with InP and selected from an MgZnSeTe-based compound semiconductor, an MgZnCdSe-based compound semiconductor, and an MgCdSSe-based compound semiconductor.
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: January 23, 2001
    Assignee: NEC Corporation
    Inventors: Koichi Naniwae, Hiroshi Iwata
  • Patent number: 6072202
    Abstract: A layer structure for a II-VI compound semiconductor device is formed on a GaAs substrate of III-V compound, wherein lattice mismatching is prevented by a first layer interposed between the GaAs substrate and a II-VI compound semiconductor active layer and made of III-V compound semiconductor including In element as a constituent element thereof. The thickness of the first layer is less than the critical thickness allowing coherent growth. Alternatively, the III-V compound of the first layer has a lattice constant substantially equal to the lattice constant of the GaAs substrate. The first layer may be a superlattice layer.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: June 6, 2000
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Patent number: 5773850
    Abstract: After the removal of a native oxide layer on a surface of an InP substrate, a ZnCdSe buffer layer is grown, and a ZnSeTe layer as a II-VI compound semiconductor layer containing Te is formed on the ZnCdSe buffer layer. This permits the ZnSeTe layer to grow two-dimensionally from directly after the start of growing such that its crystal quality is considerably improved. In this manner, a semiconductor device is attained which has above the InP substrate the II-VI compound semiconductor layer containing Te, which has such a high quality as to permit the semiconductor device to be used as a light emitting device.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: June 30, 1998
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae