Patents by Inventor Koichi Oguchi

Koichi Oguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7169621
    Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: January 30, 2007
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
  • Patent number: 6913937
    Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: July 5, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
  • Patent number: 6791863
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Publication number: 20040161887
    Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.
    Type: Application
    Filed: February 19, 2004
    Publication date: August 19, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
  • Publication number: 20040109341
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Application
    Filed: November 19, 2003
    Publication date: June 10, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Patent number: 6727536
    Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: April 27, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
  • Patent number: 6690598
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Grant
    Filed: July 2, 2001
    Date of Patent: February 10, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Publication number: 20040014247
    Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 22, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
  • Patent number: 6617627
    Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance or load capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: September 9, 2003
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
  • Publication number: 20020036934
    Abstract: A ferroelectric memory device of the present invention includes a memory cell array in which memory cells are arranged in a matrix having first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and a ferroelectric layer disposed at least in intersection regions between the first signal electrodes and the second signal electrodes, and a peripheral circuit section for selectively writing information into or reading information from the memory cell. The memory cell array and the peripheral circuit section are formed in different layers. The peripheral circuit section is formed in a region outside the memory cell array.
    Type: Application
    Filed: August 23, 2001
    Publication date: March 28, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazumasa Hasegawa, Eiji Natori, Takao Nishikawa, Koichi Oguchi, Tatsuya Shimoda
  • Publication number: 20020031005
    Abstract: The present invention relates to: a memory cell array which is capable of decreasing the parasitic capacitance of signal electrodes and has ferroelectric layers making up ferroelectric capacitors and having a predetermined pattern; a method of fabricating the memory cell array, and a ferroelectric memory device. In the memory cell array, memory cells formed of ferroelectric capacitors are arranged in a matrix. The ferroelectric capacitors include first signal electrodes, second signal electrodes arranged in a direction intersecting the first signal electrodes, and ferroelectric layers disposed linearly along either the first signal electrodes or the second signal electrodes. Alternatively, the ferroelectric layers may be disposed only in intersection areas of the first and second signal electrodes.
    Type: Application
    Filed: August 20, 2001
    Publication date: March 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Eiji Natori, Kazumasa Hasegawa, Koichi Oguchi, Takao Nishikawa, Tatsuya Shimoda
  • Publication number: 20020017667
    Abstract: A ferroelectric memory according to the present invention includes a passive matrix array in which memory cells formed of ferroelectric capacitors are arranged, and a peripheral circuit for the passive matrix array. The passive matrix array is formed of a passive matrix array microchip, and the peripheral circuit such as a word line driver circuit or a bit line driver circuit is formed on a peripheral circuit substrate, thereby integrating the passive matrix array microchip on the peripheral circuit substrate. Since this allows the passive matrix array and the peripheral circuit therefor to be separately fabricated, the peripheral circuit is not adversely affected when fabricating the passive matrix array, thereby decreasing the degree of limitation in the fabrication process.
    Type: Application
    Filed: June 28, 2001
    Publication date: February 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Tatsuya Shimoda, Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa, Atsushi Takakuwa
  • Publication number: 20020018357
    Abstract: A ferroelectric memory device includes a memory cell array and a peripheral circuit section. The memory cell array, in which memory cells are arranged in a matrix, includes first signal electrodes, second signal electrodes which are arranged in a direction so as to intersect the first signal electrodes, and a ferroelectric layer disposed at least at intersection regions between the first signal electrodes and the second signal electrodes. The peripheral circuit section includes circuits for selectively allowing information to be written into or read from the memory cells, such as a first driver circuit, a second driver circuit, and a signal detection circuit. The memory cell array and the peripheral circuit section are disposed in different layers so as to be layered. This ferroelectric memory device can significantly increase the degree of integration of the memory cells and decrease the chip area.
    Type: Application
    Filed: July 2, 2001
    Publication date: February 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Koichi Oguchi, Eiji Natori, Kazumasa Hasegawa
  • Patent number: 4648691
    Abstract: A liquid crystal display device wherein display elements are arranged in a matrix display on a substrate and the display is driven in response to external display signals is provided. The display device includes a thin film layer having a rugged diffusing surface and an opposed transparent electrode plate spaced apart from the thin film layer. A guest-host liquid crystal material including a pleochroic dye is utilized. The thin film layer may be a metal film such as, aluminum, an aluminum alloy, silver or a silver alloy having a rugged surface for providing a diffused white surface formed by vaccum evaporation, sputtering, heat-treatment, recrystallization or etching.
    Type: Grant
    Filed: December 19, 1980
    Date of Patent: March 10, 1987
    Assignee: Seiko Epson Kabushiki Kaisha
    Inventors: Koichi Oguchi, Minoru Hosokawa, Satoru Yazawa, Mitsuo Nagata
  • Patent number: 4429305
    Abstract: A matrix liquid crystal display circuit includes a selecting transistor connected to the picture element and a capacitor for each picture element of the matrix. The other picture element and capacitor terminals connect to common electrodes and the transistor gates in each row connect to a common electrode. In each column a common source line connects to the sources of the transistors and a signal sampling circuit periodically applies an image signal to the source line of each column in sequence. No amplification is used between the sampling circuit and the transistor sources. Metallic leads serve as the source lines, but other circuits and components are integrated on a common substrate.
    Type: Grant
    Filed: May 29, 1980
    Date of Patent: January 31, 1984
    Assignee: Kabushiki, Kaisha Suwa Seikosha
    Inventors: Minoru Hosokawa, Koichi Oguchi, Satoru Yazawa