Patents by Inventor Koichi Okazawa
Koichi Okazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100306438Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: August 13, 2010Publication date: December 2, 2010Applicant: HITACHI, LTD.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7802045Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: July 13, 2009Date of Patent: September 21, 2010Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7711817Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: GrantFiled: October 1, 2008Date of Patent: May 4, 2010Assignee: Hitachi, Ltd.Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Publication number: 20090276557Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.Type: ApplicationFiled: July 13, 2009Publication date: November 5, 2009Applicant: HITACHI, LTD.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7577781Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: May 29, 2008Date of Patent: August 18, 2009Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20090037578Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: ApplicationFiled: October 1, 2008Publication date: February 5, 2009Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Patent number: 7447708Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: GrantFiled: February 10, 2005Date of Patent: November 4, 2008Assignee: Hitachi, Ltd.Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Publication number: 20080244124Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween.Type: ApplicationFiled: May 29, 2008Publication date: October 2, 2008Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7398346Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 6, 2006Date of Patent: July 8, 2008Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7340552Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: December 21, 2006Date of Patent: March 4, 2008Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20070106832Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: ApplicationFiled: December 21, 2006Publication date: May 10, 2007Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Patent number: 7177970Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.Type: GrantFiled: October 22, 2002Date of Patent: February 13, 2007Assignee: Hitachi, Ltd.Inventors: Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi
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Publication number: 20070033316Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: October 6, 2006Publication date: February 8, 2007Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 7152130Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: January 11, 2005Date of Patent: December 19, 2006Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20050149580Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: ApplicationFiled: February 10, 2005Publication date: July 7, 2005Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Patent number: 6907489Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: February 27, 2004Date of Patent: June 14, 2005Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20050125585Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: January 11, 2005Publication date: June 9, 2005Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Patent number: 6868446Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.Type: GrantFiled: January 6, 2003Date of Patent: March 15, 2005Assignee: Hitachi, Ltd.Inventors: Ryuichi Hattori, Toshihiko Ogura, Takashi Oeda, Koichi Okazawa, Hideki Osaka, Tsunehiro Tobita, Tsutomu Hara
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Patent number: 6810461Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: GrantFiled: October 24, 2001Date of Patent: October 26, 2004Assignee: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida
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Publication number: 20040168007Abstract: A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.Type: ApplicationFiled: February 27, 2004Publication date: August 26, 2004Applicant: Hitachi, Ltd.Inventors: Koichi Okazawa, Koichi Kimura, Hitoshi Kawaguchi, Ichiharu Aburano, Kazushi Kobayashi, Tetsuya Mochida