Patents by Inventor Koichi Sawahata
Koichi Sawahata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7875902Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.Type: GrantFiled: November 29, 2007Date of Patent: January 25, 2011Assignee: Renesas Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata
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Publication number: 20080277689Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.Type: ApplicationFiled: November 29, 2007Publication date: November 13, 2008Applicant: NEC ELECTRONICS CORPORATIONInventors: Noriyuki Kodama, Koichi Sawahata
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Patent number: 7332748Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.Type: GrantFiled: December 3, 2003Date of Patent: February 19, 2008Assignee: NEC Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata
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Patent number: 7196377Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.Type: GrantFiled: April 22, 2005Date of Patent: March 27, 2007Assignee: NEC Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata, Morihisa Hirata
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Patent number: 7098510Abstract: A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j?1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.Type: GrantFiled: July 22, 2004Date of Patent: August 29, 2006Assignee: NEC Electronics CorporationInventors: Noriyuki Kodama, Koichi Sawahata
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Publication number: 20050236672Abstract: In a semiconductor device having an electrostatic discharge protection arrangement, a semiconductor substrate exhibits a first conductivity type. First and second impurity regions each exhibiting a second conductivity type are formed in the semiconductor substrate. A channel region is formed in the semiconductor substrate between the first and second impurity regions. A first conductive area is defined on the first impurity region in the vicinity of the channel region. A second conductive area is defined on the first impurity region so as to be supplied with an electrostatic discharge current. A third conductive area is defined on the first impurity region to establish an electrical connection between the first and second conductive area. At least one heat-radiation area is defined in the third conductive area so as to be at least partially isolated therefrom and thermally contacted with the first conductive area.Type: ApplicationFiled: April 22, 2005Publication date: October 27, 2005Inventors: Noriyuki Kodama, Koichi Sawahata, Morihisa Hirata
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Publication number: 20050029540Abstract: A multifinger ESD protection element has between an input wiring to which a surge current is input and a reference-potential wiring, 2n-number (where n is a natural number of 2 or greater) of fingers F1 to F2n. A drain resistor Rdi (i=1 to 2n), NMOS transistor Ti and source resistor Rsi are connected serially in each finger Fi in the order mentioned. A single unit Uj is constructed by two mutually adjacent fingers F2j?1 and F2j (where j is a natural number of 1 to n). In each unit the source of one transistor is connected to the gate of the other transistor and the source of this other transistor is connected to the gate of the first-mentioned transistor. The source S2j of finger F2j is connected to the source S2j+1 of the next unit Un+1. The 2n-number of fingers are connected in the form of a ring.Type: ApplicationFiled: July 22, 2004Publication date: February 10, 2005Applicant: NEC ELECTRONICS CORPORATIONInventors: Noriyuki Kodama, Koichi Sawahata
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Publication number: 20040136127Abstract: An electro-static discharge protection device includes a first conductive type well and a second conductive type well which are formed in a surface of the first conductive type layer or a first conductive type substrate. A first high concentration second conductive type region, a first high concentration first conductive type region, and a second high concentration second conductive type region are formed in a surface of the second conductive type well. A third high concentration second conductive type region is formed in a surface of the first conductive type well. The first high concentration second conductive type region and the first high concentration first conductive type region are connected with a first power supply of a potential. The third high concentration second conductive type region is connected with a second power supply having a potential different from the potential of the first power supply.Type: ApplicationFiled: December 3, 2003Publication date: July 15, 2004Inventors: Noriyuki Kodama, Koichi Sawahata
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Patent number: 6684181Abstract: The results of conventional analytical ion implantation simulation for the point defect distribution, for a silicon substrate on which an oxide layer or a nitride layer is formed, differ from the results of the Monte Carlo ion implantation simulation method. According to the present invention, it is unnecessary to distinguish between layers of materials in which point defects are or are not generated when determining the point defect distribution because, although point defects do not occur in some materials, such as oxides or nitrides, layers of these materials undergo the same amount of damage by ion implantation as layers of a material in which point defects are generated, such as silicon.Type: GrantFiled: May 12, 1999Date of Patent: January 27, 2004Assignee: NEC Electronics CorporationInventor: Koichi Sawahata
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Patent number: 6624479Abstract: A protective circuit in a semiconductor device includes a protective n-channel MOS transistor connected between the power source line and the ground line, with the gate and drain being connected together, and an n-p-n transistor having a base connected to the source of the protective n-channel MOS transistor and connected between the power source line and the ground line. The protective circuit disposed in a low-voltage semiconductor device has a lower power dissipation due to a low junction leakage current.Type: GrantFiled: April 18, 2001Date of Patent: September 23, 2003Assignee: NEC Electronics CorporationInventor: Koichi Sawahata
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Publication number: 20010033003Abstract: A protective circuit in a semiconductor device includes a protective n-channel MOS transistor connected between the power source line and the ground line, with the gate and drain being connected together, and an n-p-n transistor having a base connected to the source of the protective n-channel MOS transistor and connected between the power source line and the ground line. The protective circuit disposed in a low-voltage semiconductor device has a lower power dissipation due to a low junction leakage current.Type: ApplicationFiled: April 18, 2001Publication date: October 25, 2001Inventor: Koichi Sawahata
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Patent number: 5999719Abstract: An ion implantation process simulation device includes a Dual Pearson data extracting unit for generating a Dual Pearson data table from ion implantation profile data, a Dual Pearson data for interpolation obtaining unit for obtaining a parameter for use in the interpolation and extrapolation of a dose coefficient from the Dual Pearson data table, a dose coefficient interpolating/extrapolating unit for expressing an ion implantation profile by linear connection of two functions respectively representing an amorphous component and a channeling component, as well as using a dose-independent moment parameter and a coefficient of linear connection dependent on dose to interpolate and extrapolate a logarithmic value of a channeling component dose coefficient with respect to logarithmic values of all dose values, and a simulation result outputting unit for outputting a simulation result.Type: GrantFiled: February 26, 1998Date of Patent: December 7, 1999Assignee: NEC CorporationInventors: Susumu Asada, Koichi Sawahata
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Patent number: 5977551Abstract: On simulating ion implantation on the basis of Monte Carlo method, a plurality of triangle meshes are produced to a polygonal substrate to be label serial numbers at a first step. An ion is implanted as an implanted ion to the polygonal substrate at a second step. At a third step, the triangle meshes are checked in an ascending order until one of triangle meshes is found as a specific triangle mesh in which the implanted ion is positioned. Point defect concentration is extracted from the specific triangle mesh at a fourth step. Random numbers are generated in order to calculate scattering of the implanted ion a fifth step. The point defect concentration is renewed into a renewed point defect concentration in the specific triangle mesh at a sixth step. The energy, the position, and the travelling direction is renewed in the implanted ion at a seventh step. The third to the seventh steps is repeated until the implanted ion stops in said polygonal substrate.Type: GrantFiled: October 30, 1997Date of Patent: November 2, 1999Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5933359Abstract: An ion-implantation simulation method including (1) a step of generating orthogonal meshes for a multilayer-structure substrate, (2) a step of taking out a longitudinal strip, (3) a step of determining a function representing an impurity distribution in the longitudinal strip, (4) a step of integrating the function representing the impurity distribution in the range of each cell in the longitudinal strip, and dividing the integration value by the integration range to set the division result as the impurity concentration in the cell, (5) a step of taking out a transverse strip, (6) a step of determining a function of re-distributing the impurity distribution in the transverse strip in the transverse direction, and (7) a step of integrating the re-distributing function in the range of each cell in the transverse direction, dividing the integration result by the integration range and setting the division result as the impurity concentration in the cell.Type: GrantFiled: March 26, 1998Date of Patent: August 3, 1999Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5932881Abstract: In a computer-implemented simulation method for implanting ions into a semiconductor substrate, a region is defined in a vertical cross-section of the substrate between first and second horizontal lines, the first horizontal line being spaced a distance R.sub.p -N.sigma. from a top surface of the substrate and the second horizontal line being spaced a distance R.sub.p +N.sigma. from the top surface, where R.sub.p is a projected range of implanted ions from the top surface, N is an integer, and .sigma. is a standard deviation of horizontal spread of an impurity profile. An orthogonal coordinate system is then defined by a set of narrowly spaced horizontal parallel lines within the region, a set of widely spaced horizontal parallel lines outside of the region and a set of vertical parallel lines at spacing which increases as a function of distance from opposite vertical edges of the coordinate system.Type: GrantFiled: January 31, 1997Date of Patent: August 3, 1999Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5912824Abstract: Disclosed is an ion implantation simulation method including calculating a particle scattering process of each of sample particles as a simulation target using a Monte Carlo method, determining that the particle has stopped when scattering calculation gives zero energy of the particle, continuously performing the scattering calculation when the energy is not 0. When the scattering calculation yields an energy of the particle that has decreased to .alpha. (0.ltoreq..alpha..ltoreq.1) times the energy value at the time of implantation, the particle Is divided into a predetermined number N (N is an integer) such that the weight of the particle after division becomes 1/N that before division. The scattering calculation and the particle division process is repeated until particles having non-zero energy values are divided the predetermined number of times M (M is an integer) counting from the first division, and consequently, the weight of the particle becomes 1/N.sup.Type: GrantFiled: September 17, 1997Date of Patent: June 15, 1999Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5859784Abstract: A method for simulating an impurity distribution in a multilayer structure includes analytically simulating an impurity distribution for each layer to obtain a first impurity distribution profile for each layer by using impurity distribution moments defined for the material of each layer, analytically simulating a point defect distribution for a crystal layer to obtain a point defect distribution profile by using the first impurity distribution profile and point defect distribution moments defined for the material of crystal layer, simulating a thermal diffusion to obtain a final impurity distribution profile for each layer by using the first impurity distribution profile and point defect distribution profile. The point defect distribution moments are obtained previously for the material of the crystal layer by Monte Carlo method under typical conditions to obviate using the Monte Carlo method for each simulation under a specified condition.Type: GrantFiled: July 26, 1996Date of Patent: January 12, 1999Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5737250Abstract: An ion implantation simulation system includes a grid generating portion for generating an orthogonal grid with respect to a two-dimensional configuration of a simulation object, an elongated segment extracting portion for extracting elongated segments defined by two grid lines in the orthogonal grid, a cell analyzing portion for extracting cells defined by adjacent grid lines perpendicular to the longer edge of the elongated segment, in the extracted elongated segments, and linearly rearranging polygon elements presenting in the cell along the longer edge direction, simulation performing portion performing linear ion implantation simulation with respect to the cell, in which the polygon elements are linearly rearranged, and a calculation result registering portion for registering an impurity concentration obtained as a result of simulation for each polygon element and registering the impurity concentration in each polygon element.Type: GrantFiled: October 12, 1995Date of Patent: April 7, 1998Assignee: NEC CorporationInventor: Koichi Sawahata
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Patent number: 5502654Abstract: A novel method for analyzing a light intensity distribution on a flat surface in a projection system wherein a pattern is projected by use of a light through a pupil on the flat surface. The pattern is analyzed into plural polygonal elements where a combination of the polygonal elements constitutes the pattern. Fourier transformations of vertexes of each of the polygonal elements except for the pattern are calculated for subsequent addition and subtraction of the Fourier transformations of all the polygonal elements to thereby obtain a Fourier transformation of the pattern. A product of the Fourier transformation of the pattern and a pupil function is calculated for the pupil. An invert Fourier transformation of the product is calculated to thereby obtain a light intensity distribution.Type: GrantFiled: October 31, 1994Date of Patent: March 26, 1996Assignee: NEC CorporationInventor: Koichi Sawahata