Abstract: According to one embodiment, an electronic device includes a receptacle, a first port, a second port, and a switch circuit. The receptacle includes pins. The pins of the receptacle are connectable to pins of a plug respectively. Each of the first and second ports communicates with the receptacle. The switch circuit switches a signal flow between the receptacle, and the first port and second port when the plug is inserted into the receptacle. The switch circuit communicates a first signal between the first port and one of a pair of first and second pins of the receptacle and a pair of third and fourth pins of the receptacle, and communicates a second signal between the second port and the other of the pair of the first and second pins and the pair of the third and fourth pins.

Abstract: According to one embodiment, a system includes first and second devices. The first device detects whether a cable is connected to the first device in a first state or a second state. The first device receives, from the second device, status information indicative of whether the cable is connected to the second device in the first state or the second state. The first device switches allocation of signal lines to contact pins of a connector of the first device to which the cable is connected, based on connection states of the first and second devices. The second device detects whether the cable is connected to the second device in the first state or the second state. The second device transmits, to the first device, a result of detection as the status information.

Abstract: According to one embodiment, an electronic device includes a receptacle, a first port, a second port, and a switch circuit. The receptacle includes pins. The pins of the receptacle are connectable to pins of a plug respectively. Each of the first and second ports communicates with the receptacle. The switch circuit switches a signal flow between the receptacle, and the first port and second port when the plug is inserted into the receptacle. The switch circuit communicates a first signal between the first port and one of a pair of first and second pins of the receptacle and a pair of third and fourth pins of the receptacle, and communicates a second signal between the second port and the other of the pair of the first and second pins and the pair of the third and fourth pins.

Abstract: According to one embodiment, a system includes first and second devices. The first device detects whether a cable is connected to the first device in a first state or a second state. The first device receives, from the second device, status information indicative of whether the cable is connected to the second device in the first state or the second state. The first device switches allocation of signal lines to contact pins of a connector of the first device to which the cable is connected, based on connection states of the first and second devices. The second device detects whether the cable is connected to the second device in the first state or the second state. The second device transmits, to the first device, a result of detection as the status information.

Abstract: According to one embodiment, a switching circuit includes a device, a load switch, a device bus to which the device is connected, a device bus terminating resistor, a bus switch, and a host bus terminating resistor. The load switch feeds power to the device when a control signal is active. The device bus terminating resistor terminates the device bus. The bus switch connects a host bus and the device bus when the control signal is active or when the load switch is in a feed state. The host bus terminating resistor terminates the host bus when the host bus and the device bus are disconnected.

Abstract: According to one exemplary embodiment, an electronic apparatus includes: a controller which determines whether to display 2D video or 3D video as video corresponding to a video signal according to a size of a display window in which the video corresponding to the video signal is to be displayed; an image processor which generates 2D video data or 3D video data based on the video signal according to a determination result of the controller; and a display module which displays, in the display window, any one of 2D video corresponding to the 2D video data and 3D video corresponding to the 3D video data.

Abstract: A first comparator makes a comparison between potentials on paired signal lines connected with the secondary winding of a transformer to produce a signal indicating whether data of a first value has been received or not. A second comparator makes a comparison between potentials on the paired signal lines to output a signal indicating whether data of a second value has been received or not. A first detector samples the output signal of the first comparator at regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the first value has been produced from the first comparator. A second detector samples the output signal of the second comparator at the regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the second value has been produced from the second comparator.

Abstract: A first comparator makes a comparison between potentials on paired signal lines connected with the secondary winding of a transformer to produce a signal indicating whether data of a first value has been received or not. A second comparator makes a comparison between potentials on the paired signal lines to output a signal indicating whether data of a second value has been received or not. A first detector samples the output signal of the first comparator at regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the first value has been produced from the first comparator. A second detector samples the output signal of the second comparator at the regular sampling intervals to produce a signal indicating whether an output signal indicating the reception of data of the second value has been produced from the second comparator.

Abstract: The CPU speed is apparently decreased, and current consumption is reduced by asserting a stop clock (STPCLK#) signal at a predetermined interval. When a system event (INTR, NMI, SMI, SRESET, and INIT) occurs, assertion of the STPCLK# signal is inhibited for a predetermined time to allow a high-speed operation. In an ISA refresh cycle, by asserting the STPCLK# signal instead of a conventional HOLD/HLDA cycle, the refresh cycle is executed in a stop grant state.

Abstract: There is provided a computer system including a system memory operable with a first voltage level, a processor operable with a second voltage level different from the first voltage level, and capable of accessing the system memory to perform burst read, a data bus connected to the processor, and a level shifter connected between the system memory and the data bus for shifting the voltage level of a data signal supplied from the system memory and transferring the level-shifted data signal to the data bus, the level shifter including a latch circuit for sequentially latching, at predetermined interval, a plurality of n-bit data which constitute the level-shifted data signal, to thereby minimize the interval between each adjacent pair of the n-bit data.

Abstract: A global standby System Management Interrupt ("SMI) is supplied to a CPU when all hardware interrupt requests (except a timer interrupt) are not generated for four seconds. The SMI routine sets the CPU to a stop grant state whereby the CPU goes to a sleep mode. Thus, the same sleep mode function is provided regardless of the operating system environment. Memory banks are reallocated in the DRAM logical address space in memory-size order such that a smaller address range is allocated to a bank with a larger memory size. For any address range allocated to any DRAM bank, there is a sequence of bits having a common value associated with all the memory address values belonging to the address range. Each sequence of bits is used as a decoding condition for the associated address strobe line. The memory address space of the CPU is separated into a plurality of memory address areas.