Patents by Inventor Koichi SHIRAHATA

Koichi SHIRAHATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200310874
    Abstract: A scheduler includes circuitry configured to, based on similarity between execution time and power consumption information of jobs executed in a system, classifies jobs into groups, construct respective time series prediction models for the groups using a power waveform included in each of the groups as teacher data, predict a power waveform at an interval including a first time from each of the constructed time series prediction models, compare a power waveform at an interval including a first time of a job in execution for which power is to be predicted with the predicted power waveform of each of the groups to identify a similar time series prediction model, based on the identified time series prediction model, predict power consumption at a predetermined interval including a second time for the job for which power is to be predicted, and control job execution based on the predicted power consumption.
    Type: Application
    Filed: March 4, 2020
    Publication date: October 1, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takashi Shiraishi, Shigeto SUZUKI, Koichi SHIRAHATA
  • Publication number: 20200257605
    Abstract: A non-transitory computer-readable recording medium has stored therein a program that causes a computer to execute a process including: dividing a time from a start to an end of execution of a first job into a plurality of time periods, the time being represented in first power consumption information; calculating a cycle of a time-series variation of power consumption within each time period; generating, for each of the plurality of time periods, a prediction model for predicting power consumption of a predetermined future time; acquiring second power consumption information that is an actual measurement value of power consumption according to an elapsed time from a start of execution of a second job that is being executed; and predicting future power consumption of the second job, using the prediction model generated for a time period including the elapsed time from the start of execution of the second job to a present.
    Type: Application
    Filed: January 24, 2020
    Publication date: August 13, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Shigeto SUZUKI, Michiko SHIRAGA, Koichi SHIRAHATA, Hiroshi ENDO, Hiroyuki FUKUDA, Takuji YAMAMOTO
  • Publication number: 20200202222
    Abstract: An information processing method includes: deciding a timing when transfer to a memory is completed in a total time that is a sum of a calculation time at one or plurality of second layers at which calculation is carried out earlier than a first layer regarding a timing when data relating to calculation of the first layer is stored in the memory based on a calculation time estimated in advance regarding each of one layer or a given number of layers in a plurality of layers included in a neural network and a time of transfer of data relating to calculation of each of the one layer or the given number of layers to the memory; and storing the data relating to calculation of the first layer in the memory based on the decided timing in sequentially carrying out calculation of each layer of the neural network.
    Type: Application
    Filed: November 18, 2019
    Publication date: June 25, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Koichi SHIRAHATA
  • Publication number: 20200202201
    Abstract: An information processing apparatus includes a processor including a first operation circuit that executes a product-sum operation, a second operation circuit that executes a certain operation, and a resister. The processor executes a first operation including the certain operation in a first layer in a neural network. The processor executes the first operation by a second method of calculating the certain operation by the second operation circuit, in a case where second operation time necessary for the first operation when the certain operation is executed by the second operation circuit is less than memory transfer time. Or the processor executes the first operation by a first method of calculating the certain operation by an approximate calculation by the first operation circuit, in a case where first operation time necessary for the first operation when executed by the first method is less than the memory transfer time.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 25, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Koichi SHIRAHATA, Takashi Arakawa, Katsuhiro Yoda, MAKIKO ITO, YASUMOTO TOMITA
  • Publication number: 20200074690
    Abstract: An image recognition apparatus includes a processor including a plurality of arithmetic units; and a memory storing a plurality of data elements, each corresponding to one of candidate regions detected in an image and indicating a location and an evaluation value of the corresponding candidate region. The processor sorts the data elements by calculating in parallel, in reference to evaluation values, indexes each indicating a position of a corresponding one of the data elements in a sorted ordering and transferring in parallel, after the calculation of the indexes, the data elements based on the indexes. The processor selects part of the candidate regions based on the sorted ordering of the data elements.
    Type: Application
    Filed: August 19, 2019
    Publication date: March 5, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Takuya Fukagai, Kyosuke MAEDA, Koichi SHIRAHATA, YASUMOTO TOMITA
  • Patent number: 10296804
    Abstract: An image recognizing apparatus includes a processor that controls first and second learning processes, the first learning process in second layers including holding, based on a large/small relation between neuron data size and parameter size of the second layer, in a memory area, an error gradient of parameters to be sent to the corresponding layer of the second layers; and the second learning process between first layers including holding, in a memory area of each first layers, an error gradient of parameters to be sent to the corresponding layer of the first layers, which is computed based on the error gradient or an error gradient of a previous layer of the first layers, based on a large/small relation between neuron data size and parameter size of the first layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Koichi Shirahata
  • Publication number: 20180330229
    Abstract: An information processing apparatus includes a memory and a processor coupled to the memory and configured to set a first memory region in the memory as a region to be used for input to a first intermediate layer of a layered neural network and for output from the first intermediate layer, set a second memory region in the memory as a buffer region for the first intermediate layer, execute a recognition process of storing, in the second memory region, characteristic data corresponding to a characteristic of an input neuron data item to the first intermediate layer, and execute a learning process of determining an error of the first intermediate layer using the characteristic data stored in the second memory region.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 15, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Koichi Shirahata
  • Publication number: 20180150745
    Abstract: An information processing device includes: a processor that executes a process, the process including: controlling a recognition process that performs, with respect to input neuron data, a hierarchical neural network operation including a weighting operation using a parameter and that holds the neuron data and the parameter of each layer of the neural network in each of memory areas; and performing, in a learning process of learning the parameter of each layer of the neural network from an error that is obtained from a recognition result, regarding the layer in which the neuron data and the parameter are held in the memory areas, control of calculating an error of the neuron data after calculating an error of the parameter.
    Type: Application
    Filed: October 2, 2017
    Publication date: May 31, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Koichi SHIRAHATA
  • Publication number: 20180032835
    Abstract: An image recognizing apparatus includes a processor that controls first and second learning processes, the first learning process in second layers including holding, based on a large/small relation between neuron data size and parameter size of the second layer, in a memory area, an error gradient of parameters to be sent to the corresponding layer of the second layers; and the second learning process between first layers including holding, in a memory area of each first layers, an error gradient of parameters to be sent to the corresponding layer of the first layers, which is computed based on the error gradient or an error gradient of a previous layer of the first layers, based on a large/small relation between neuron data size and parameter size of the first layer.
    Type: Application
    Filed: June 20, 2017
    Publication date: February 1, 2018
    Applicant: FUJITSU LIMITED
    Inventor: Koichi SHIRAHATA