Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.

Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.

Abstract: A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.

Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.

Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .

Abstract: A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.

Abstract: A semiconductor wafer is disclosed that includes a substrate; a plurality of device chip areas formed on the substrate; a plurality of scribe lines formed in a lattice-like manner on the substrate, the scribe lines being provided so as to separate the device chip areas from each other; a blank area in which at least one alignment mark formed of a metal film for alignment of the semiconductor wafer is formed, the blank area being provided in an area different from the device chip areas; and a scribe area in which the alignment mark is prevented from existing, the scribe area being provided in each area where the blank area crosses the scribe lines.

Abstract: A method of detecting a position of a size check pattern on a substrate by using a size check apparatus so as to measure a size of the size check pattern for a purpose of checking precision of production, comprising the steps of a) providing image recognition assisting patterns on the substrate on both sides of a portion to be measured of the size check pattern, b) setting the size check apparatus to have an image recognition area that includes both the size check pattern and the image recognition assisting patterns, and c) detecting the position of the size check pattern by use of the size check apparatus based on the size check pattern and the image recognition assisting patterns.

Abstract: A method of detecting a position of a size check pattern on a substrate by using a size check apparatus so as to measure a size of the size check pattern for a purpose of checking precision of production, comprising the steps of a) providing image recognition assisting patterns on the substrate on both sides of a portion to be measured of the size check pattern, b) setting the size check apparatus to have an image recognition area that includes both the size check pattern and the image recognition assisting patterns, and c) detecting the position of the size check pattern by use of the size check apparatus based on the size check pattern and the image recognition assisting patterns.

Abstract: An overlay target for the precision measurement is provided, including a substrate box formed over or in a substrate and a top box formed over the substrate box 13 and the substrate. The substrate box is of square with its side of 10 microns long. The top box is formed as a square opening composed of a layer of either a positive or negative type photo-resist with its side 10 microns long. These boxes are disposed rotated by 45.degree. with respect to each other and the centers of the box marks are aligned during process steps to coincide with each other to thereby result in a minimal amount of displacement, if any, between the centers. Following the measurements of the lengths of the sections a, b, c and d, which are defined by the overlap between the top and substrate boxes on the confronting sides, amounts of displacement between the centers of the two boxes are determined using the relationships, X.sub.reg =(b-a)/4 and Y.sub.reg =(d-c)/4.

Abstract: In a semiconductor device, N-type diffusion regions for providing an LDD structure are formed on a P-type substrate. A thick CVD deposited insulating film is formed on both the diffusion regions. A word line layer is formed on this deposited insulating film and a gate oxide film in a direction crossing the diffusion regions. Since the deposited insulating film is set to be thick, a capacity between one of the diffusion regions as a bit line layer and the word line layer is reduced so that a reading speed of the semiconductor device is improved. Further, a punch through proof pressure is increased since the diffusion regions have an LDD structure. Thus, it is possible to provide a planar cell structure which increases the reading speed and is advantageous in a fine structure. Another semiconductor device is also shown. A method for manufacturing the semiconductor device is further shown.

Abstract: A semiconductor memory device includes a substrate, a first diffusion region composed of at least one longitudinal and continuous source region which is disposed on the substrate and commonly used for a plurality of memory transistors, and a second diffusion region composed of at least one longitudinal and continuous drain region which is disposed in parallel with the first diffusion region and commonly used for the plurality of memory transistors. A refractory metal film is disposed on each of the first and second diffusion regions. An electric insulation film is disposed on the refractory metal film. A plurality of parallel gate electrodes are disposed crossing over the first and second diffusion regions. And a gate oxide film is arranged to electrically insulate the gate electrodes from the diffusion regions.

Abstract: A semiconductor memory device comprising a substrate, a longitudinal source diffusion layer for a plurality of memory transistor source regions continuously formed on the substrate, and a longitudinal drain diffusion layer for a plurality of memory transistor drain regions continuously formed on the substrate in parallel to the source diffusion layer. A word line is formed crossing over the diffusion layers. And an electrically insulating film is interposed between the word line and the diffusion layers. The insulating film is thicker than a gate oxide film formed between the diffusion layers.