Patents by Inventor Koichi Sudo

Koichi Sudo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6344857
    Abstract: A gamma correction circuit includes a node level setting unit set predetermined level values of video signals from outside, in a case where encoded M-bit (where M is an arbitrary integer) video signals being represented by using predetermined number of sections and the level values of the video signals corresponding to 2n+1 number of nodes (where n is an arbitrary integer) associated with the sections on which the node are specified, and a gamma correction unit for executing gamma correction for the M-bit video signal in accordance with the level values of the nodes set in the node level setting unit, thereby the gamma correction circuit executes gamma correction on various types of display devices.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: February 5, 2002
    Assignees: Hitachi, Ltd., Hitachi Video & Information System, Inc.
    Inventors: Takaaki Matono, Haruki Takata, Katsunobu Kimura, Tatsuo Nagata, Takeshi Sakai, Koichi Sudo
  • Patent number: 6195132
    Abstract: A noise reduction signal processing apparatus for reducing noises accurately, such as for use in a display apparatus for displaying a video signal, has a median filter (40) which receives the video signal, and which executes a filter processing on the inputted video signal and outputs a reference signal; a subtracter (50) which is connected with the median filter (40), and which outputs a difference signal that indicates a difference between a reference signal outputted from the median filter (40) and the video signal; a minimum value detection circuit (70) which outputs the difference signal from the subtracter (50) or a limitation value, whichever is smaller, as a minimum value signal; and an adder (35) which adds a noise reduction signal obtained on the basis of the minimum value signal output from the minimum value detection circuit (70) and the video signal.
    Type: Grant
    Filed: July 1, 1999
    Date of Patent: February 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Katsunobu Kimura, Takaaki Matono, Haruki Takata, Tatsuo Nagata, Masato Sugiyama, Yasutaka Tsuru, Koichi Sudo
  • Patent number: 6151079
    Abstract: The present invention relates to a video signal processing apparatus for converting video signals based on a desired transmission system such as NTSC, PAL, MUSE or any other system so as to conform to a display unit of a desired screen system such as XGA, VGA or the like. The apparatus has a feature that it is provided with a PLL circuit for changing a sampling frequency used by an analog-to-digital converter for converting inputted video signals into digital signals in accordance with the sort of the transmission system of the video signals, and a controller for controlling picture element interpolation of the digital signals performed by a picture image magnifying circuit for magnifying the video signals horizontally and vertically, in accordance with the sort of the transmission system of the video signals.
    Type: Grant
    Filed: July 23, 1999
    Date of Patent: November 21, 2000
    Assignees: Hitachi, Ltd., Hitachi Video & Information System, Inc.
    Inventors: Tatsuo Nagata, Takaaki Matono, Takeshi Sakai, Ryo Hasegawa, Koichi Sudo
  • Patent number: 6078702
    Abstract: The present invention is concerned with image display apparatus capable of displaying the image of each of a television signal (TV signal) and an image signal (PC signal) from a personal computer. In addition, the present invention is to improve the performance of such apparatus, particularly to prevent the image from being deteriorated when the pixel number is converted, or changed to increase the pixel number of each of the TV signal and PC signal. In order to achieve this, the apparatus according to the invention has its pixel number conversion circuit provided with a plurality of conversion modes of different systems so that the pixel number conversion can be performed by properly switching the conversion modes in accordance with the type of the input image signal.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: June 20, 2000
    Assignees: Hitachi, Ltd., Hitachi Video & Information Systems, Inc.
    Inventors: Takaaki Matono, Tatsuo Nagata, Takeshi Sakai, Koichi Sudo
  • Patent number: 5953075
    Abstract: The present invention relates to a video signal processing apparatus for converting video signals based on a desired transmission system such as NTSC, PAL, MUSE or any other system so as to conform to a display unit of a desired screen system such as XGA, VGA or the like. The apparatus has a feature that it is provided with a PLL circuit for changing a sampling frequency used by an analog-to-digital converter for converting inputted video signals into digital signals in accordance with the sort of the transmission system of the video signals, and a controller for controlling picture element interpolation of the digital signals performed by a picture image magnifying circuit for magnifying the video signals horizontally and vertically, in accordance with the sort of the transmission system of the video signals.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: September 14, 1999
    Assignees: Hitachi, Ltd., Hitachi Video and Information System, Inc.
    Inventors: Tatsuo Nagata, Takaaki Matono, Takeshi Sakai, Ryo Hasegawa, Koichi Sudo
  • Patent number: 5838381
    Abstract: The present invention aims at providing an image display apparatus capable of displaying both a television signal and an image signal supplied from a personal computer with a high picture quality on a high definition display unit having 1024 by 768 pixels. In order to achieve this object, an image display apparatus according to the present invention includes an NTSC-VGA conversion circuit for converting a television signal to a signal having 640 by 480 pixels and corresponding to the non-interlacing VGA standard, a switch unit for selecting and outputting either the signal outputted from the NTSC-VGA conversion circuit and an inputted image signal from a personal computer, and a VGA-XGA conversion circuit for converting a number of pixels of a signal outputted from the switch unit to a number of pixels 1024 by 768 substantially equivalent to the number of the display unit.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: November 17, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Kasahara, Takaaki Matono, Koichi Sudo, Makoto Kitamura, Yasuhiro Tomita, Kouichi Sugimoto, Toshihiko Matsuzawa, Fumiyoshi Akiyama
  • Patent number: 5306568
    Abstract: A high Young's modulus material comprises carbon steel or alloying steel and contains a particular amount of hard particles having a Young's modulus of not less than 24,000 kgf/mm.sup.2. Furthermore, a surface-coated tool member comprises a substrate comprised of carbon steel or alloying steel and a hard coating layer having a Young's modulus of not less than 24,000 kgf/mm.sup.2 in which the substrate contains a particular amount of hard particles having a Young's modulus of not less than 24,000 kgf/mm.sup.2.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: April 26, 1994
    Assignee: Daido Tokushuko Kabushiki Kaisha
    Inventors: Yukinori Matsuda, Kozo Ozaki, Koichi Sudo
  • Patent number: 5160675
    Abstract: A sputter target for producing electroconductive transparent films, which comprises indium oxide and tin oxide and having a shape such that not less than 80% by weight of the target is present in an erosion area on sputtering, and a process for manufacturing the sputtering target which comprises molding a slurry or a powder mixture containing indium oxide and tin oxide into a molded shape and sintering the molded shape are disclosed.
    Type: Grant
    Filed: May 16, 1989
    Date of Patent: November 3, 1992
    Assignee: Tosoh Corporation
    Inventors: Tetsushi Iwamoto, Yasunobu Yoshida, Toshiaki Furuto, Koichi Sudo
  • Patent number: 5139737
    Abstract: Disclosed is a steel for plastics molds superior in weldability. The steel consists essentially of C: 0.1 to 0.3%, Mn: 0.5 to 3.5%, Cr: 1.0 to 3.0%, Mo:0.03 to 2.0%, V:0.1 to 1.0% and S: 0.01 to 0.10%; Si: not more than 0.25%, P: not more than 0.2%, and B: not more than 0.002%; the balance being substantially Fe. The alloy composition should satisfy the following formula:BH=326.0+847.3 (C%)+18.3 (Si%) -8.6 (Mn%)-12.5 (Cr%).ltoreq.460The steel can be welded in the process of manufacturing a plastics mold without reqiring preheating and postheating.
    Type: Grant
    Filed: December 5, 1990
    Date of Patent: August 18, 1992
    Assignee: Dadio Tokushuko Kabushiki Kaisha
    Inventors: Koichi Sudo, Masaru Nagata