Abstract: A tire performance testing apparatus capable of reproducing conditions in which tire runs on actual road having a pothole, that is, conditions in which tire hits projection after moving in the air. The tire performance testing apparatus includes a tire running surface, a projection installing surface disposed on the front side of the end of the tire running surface in the traveling direction of a vehicle traveling on the tire running surface and positioned lower than the end of the tire running surface, and a projection disposed on the projection installing surface in such a manner as to protrude upward from the projection installing surface. And the distance between the end of the tire running surface and the projection is so set that the tire of a vehicle traveling on the tire running surface hits the projection after getting airborne away from the end of the tire running surface.

Abstract: A tire performance testing apparatus capable of reproducing conditions in which tire runs on actual road having a pothole, that is, conditions in which tire hits projection after moving in the air. The tire performance testing apparatus includes a tire running surface, a projection installing surface disposed on the front side of the end of the tire running surface in the traveling direction of a vehicle traveling on the tire running surface and positioned lower than the end of the tire running surface, and a projection disposed on the projection installing surface in such a manner as to protrude upward from the projection installing surface. And the distance between the end of the tire running surface and the projection is so set that the tire of a vehicle traveling on the tire running surface hits the projection after getting airborne away from the end of the tire running surface.

Abstract: A communication device includes an addition unit which outputs a result of adding a predetermined number to the number of data blocks of a first signal, a comparison unit which, on the basis of comparison of the addition result with the number of data blocks of a second signal outputs the addition result of subtracting the number of data blocks of the second signal from the addition result, as a selection result, a data insertion unit which, on the basis of comparison of the selection result with the number of data blocks of the first signal, inserts either of the first signal and adjustment data into the second signal, and a storage unit which stores the selection result, and outputs the selection result stored last time to the addition unit, as the predetermined number.

Abstract: A communication device includes an addition unit which outputs a result of adding a predetermined number to the number of data blocks of a first signal, a comparison unit which, on the basis of comparison of the addition result with the number of data blocks of a second signal outputs the addition result of subtracting the number of data blocks of the second signal from the addition result, as a selection result, a data insertion unit which, on the basis of comparison of the selection result with the number of data blocks of the first signal, inserts either of the first signal and adjustment data into the second signal, and a storage unit which stores the selection result, and outputs the selection result stored last time to the addition unit, as the predetermined number.

Abstract: An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data. Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.

Abstract: A vertex sorter 114 converts a polygon structure instance into a polygon/sprite shared data Cl, and a vertex expander 116 converts a sprite structure instance into a polygon/sprite shared data Cl in the same format. Subsequent circuits 118, 120, 122, 124, 126, 11, 130 and 132 generate an image to be displayed in a screen on the basis of the polygon/sprite shared data Cl with the same format. It is possible to generate an image which is formed from any combination of polygons and sprites, while suppressing the hardware scale, and furthermore it is possible to increase the number of the polygons and sprites capable of simultaneously drawing without incurring an increased memory capacity.

Abstract: A CPU 5 is provided with both the functionality of issuing an external bus access request directly to an external memory interface 3 and the functionality of issuing a DMA transfer request to a DMAC 4. Accordingly, in the case where data is randomly accessed at discrete addresses, an external bus access request is issued directly to the external memory interface 3, and in the case of data block transfer or page swapping as requested by a virtual memory management unit or the like, a DMA transfer request is issued to the DMAC 4, so that it is possible to effectively access the external memory 50.

Abstract: A data processing unit for performing a high speed drawing operation of arbitrary patterns even in individual pixels is provided. It is assumed that the color mode is set to 3 bits per pixel. A pixel “N” is written to a drawing position designated by a byte address [29:3] and a bit address [2:0]. The subsequent pixel “N+1” is written immediately after the pixel “N”. The next subsequent pixel “N+2” is written immediately after the pixel “N+1” to span the adjacent bytes. Thereby, the pixel data is continuously stored within each byte and across the boundary between bytes with no space. In this case, the operation of writing pixel data, i.e., the drawing is performed not in words or bytes but in pixels. In addition to this, high speed drawing is possible by the use of a caching system.

Abstract: An image mixing apparatus and a pixel mixer capable of mixing image data items having different pixel resolutions, and mixing image data items in an arbitrary display priority, irrespective of the order of mixing, even if the order of mixing is determined in advance is provided. Of two pixel data items having depth values “Zc” and “Zb”, one pixel data item having the depth value indicating that the pixel is located in a foreground position is selected by a pixel selection determination circuit 110. However, if a pixel data item has a hue indicating that the pixel is transparent, such a pixel data item is not selected but another pixel data item is selected instead. Multiplexers 112 to 116 output a pixel data item (hue “Hm”/color saturation “Sm”/brightness “Lm”) which is selected by the pixel selection determination circuit 110. Since pixel data items are input to the multiplexer 112 to 116 at different output rates, it is possible to mix images having different pixel resolutions.

Abstract: An effective bus arbitration unit is described in which it is possible to reduce, as much as possible, the waiting time until a bus master obtain bus ownership and improve the rate of operating the bus while improving the throughput of data transfer. A bus master issues a size signal (for example, signal “CDSZ”) indicative of the size of data to be read or written. A state machine 155 grants bus ownership to the bus master for the bus cycles corresponding to the size signal in order to enable the bus master to successively read or write data Arbitration is performed once for every series of bus cycles corresponding to the size requested by the bus master. Since the size signal is issued by the bus master as a size signal indicative of the necessary and sufficient size for data transmission, the state machine 155 can set an optimal number of bus cycles.

Abstract: A YSU (19) sorts structure instances #0 to #7 in order that the polygons #0 to #7 corresponding thereto are arranged in ascending order of the minimum Y-coordinates thereof. An RPU (9) sequentially reads the structure instances #0 to #7 sorted by the YSU (19), and performs the drawing process of corresponding polygons on the basis of the structure instances as read.

Abstract: A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.

Abstract: An artificial snow layer 83 in which artificial snow is arranged in a layered form is provided on a turntable 72, and on-snow testing is performed by rotating the turntable 72 and rotating the tire 11 on the artificial snow layer 83. The artificial snow is made from a frozen granular water-absorbent material that has been made to absorb water. The artificial snow can be reused, and on-snow testing of the tire 11 can be performed at low cost by performing testing of the tire 11 on the turntable 72.