Abstract: A signal transmission device having a capacitor coupler includes a semiconductor substrate, a low voltage circuit region, an insulating film formed on the semiconductor substrate, a lower electrode formed on the semiconductor substrate via the insulating film, and an upper electrode disposed opposite to the lower electrode via the insulating film interposed therebetween. A shield portion includes a conductor to which a low voltage is applied is provided between the lower electrode and the upper electrode and the low voltage circuit region. When a stacking direction of the lower electrode and the upper electrode is defined as a height direction, the shield portion is located higher than the low voltage circuit region and has an eaves part extending on an opposite side with respect to the lower electrode and the upper electrode.

Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.

Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller the controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.

Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.

Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.

Abstract: A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode.

Abstract: Provided is that the method of manufacturing the semiconductor device including a first process of implanting a first impurity of a first conductivity type in a source and drain region having an elevated structure, with a concentration equal to or less than 1E14 atoms/cm2, on the conditions that the concentration peak thereof is located more deeply than the interface between silicide and a semiconductor substrate, a second process of implanting a second impurity of a first conductivity type having a smaller mass than that of the first impurity in the source and drain region on the conditions that the peak thereof is located more shallowly than the concentration peak of the first impurity, and a third process of applying high-temperature millisecond annealing to the semiconductor substrate after the first and second processes.

Abstract: Provided is that the method of manufacturing the semiconductor device including a first process of implanting a first impurity of a first conductivity type in a source and drain region having an elevated structure, with a concentration equal to or less than 1E14 atoms/cm2, on the conditions that the concentration peak thereof is located more deeply than the interface between silicide and a semiconductor substrate, a second process of implanting a second impurity of a first conductivity type having a smaller mass than that of the first impurity in the source and drain region on the conditions that the peak thereof is located more shallowly than the concentration peak of the first impurity, and a third process of applying high-temperature millisecond annealing to the semiconductor substrate after the first and second processes.