Patents by Inventor Koichi Yatsuda

Koichi Yatsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11557661
    Abstract: A method for manufacturing a semiconductor device includes: a first insulating film forming step of forming a first insulating film in a transistor having a structure in which a source and a drain raised in a fin shape are covered with a gate; a sacrifice film forming step of forming a sacrifice film; a hard mask pattern forming step of forming a hard mask film having a desired pattern; a first opening forming step of forming a first opening; a second insulating film forming step of forming a second insulating film made of a material different from the first insulating film, in the first opening; a second opening forming step of forming a second opening by removing the sacrifice film, after the second insulating film forming step; and a contact plug forming step of forming a contact plug in the second opening.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: January 17, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Koichi Yatsuda
  • Patent number: 11495490
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 8, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Tatsuya Yamaguchi, Yannick Feurprier, Frederic Lazzarino, Jean-Francois de Marneffe, Khashayar Babaei Gavan
  • Patent number: 11171050
    Abstract: A method includes a step of performing a selective catalyst treatment by supplying a catalyst solution to an upper surface of an exposed interconnection layer forming a step portion of a stepped shape formed by pair layers stacked to form the stepped shape, the pair layer including an interconnection layer formed on an insulating layer, and a step of selectively growing a metal layer by performing electroless plating on the upper surface of the interconnection layer on which the catalyst treatment is performed.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 9, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Mitsuaki Iwashita, Takashi Tanaka
  • Patent number: 11120999
    Abstract: A plasma etching method includes a physisorption step for causing an adsorbate that is based on first processing gas to be physisorbed onto a film to be etched, while cooling an object to be processed on which the film to be etched is provided; and an etching step for etching the film to be etched by causing the adsorbate to react with the film to be etched, using the plasma of second processing gas.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 14, 2021
    Assignees: TOKYO ELECTRON LIMITED, UNIVERSITE D'ORLEANS
    Inventors: Koichi Yatsuda, Kaoru Maekawa, Nagisa Sato, Kumiko Ono, Shigeru Tahara, Jacques Faguet, Remi Dussart, Thomas Tillocher, Philippe Lefaucheux, Gaëlle Antoun
  • Patent number: 11056349
    Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: July 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Hiroshi Okuno, Reiji Niino, Hiroyuki Hashimoto, Tatsuya Yamaguchi
  • Patent number: 11004684
    Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 11, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuaki Iwashita, Takeshi Nagao, Nobutaka Mizutani, Takashi Tanaka, Koichi Yatsuda, Kazutoshi Iwai, Yuichiro Inatomi
  • Publication number: 20210118727
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 22, 2021
    Inventors: Koichi YATSUDA, Tatsuya YAMAGUCHI, Yannick FEURPRIER, Frederic LAZZARINO, Jean-Francois de MARNEFFE, Khashayar BABAEI GAVAN
  • Patent number: 10910259
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignees: TOKYO ELECTRON LIMITED, IMEC VZW
    Inventors: Koichi Yatsuda, Tatsuya Yamaguchi, Yannick Feurprier, Frederic Lazzarino, Jean-Francois de Marneffe, Khashayar Babaei Gavan
  • Publication number: 20210020758
    Abstract: A method for manufacturing a semiconductor device includes: a first insulating film forming step of forming a first insulating film in a transistor having a structure in which a source and a drain raised in a fin shape are covered with a gate; a sacrifice film forming step of forming a sacrifice film; a hard mask pattern forming step of forming a hard mask film having a desired pattern; a first opening forming step of forming a first opening; a second insulating film forming step of forming a second insulating film made of a material different from the first insulating film, in the first opening; a second opening forming step of forming a second opening by removing the sacrifice film, after the second insulating film forming step; and a contact plug forming step of forming a contact plug in the second opening.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Koichi YATSUDA
  • Publication number: 20200381264
    Abstract: A plasma etching method includes a physisorption step for causing an adsorbate that is based on first processing gas to be physisorbed onto a film to be etched, while cooling an object to be processed on which the film to be etched is provided; and an etching step for etching the film to be etched by causing the adsorbate to react with the film to be etched, using the plasma of second processing gas.
    Type: Application
    Filed: December 11, 2018
    Publication date: December 3, 2020
    Applicants: TOKYO ELECTRON LIMITED, UNIVERSITE D'ORLEANS
    Inventors: Koichi YATSUDA, Kaoru MAEKAWA, Nagisa SATO, Kumiko ONO, Shigeru TAHARA, Jacques FAGUET, Remi DUSSART, Thomas TILLOCHER, Philippe LEFAUCHEUX, Gaëlle ANTOUN
  • Patent number: 10840359
    Abstract: A method for manufacturing a semiconductor device includes: a first insulating film forming step of forming a first insulating film in a transistor having a structure in which a source and a drain raised in a fin shape are covered with a gate; a sacrifice film forming step of forming a sacrifice film; a hard mask pattern forming step of forming a hard mask film having a desired pattern; a first opening forming step of forming a first opening; a second insulating film forming step of forming a second insulating film made of a material different from the first insulating film, in the first opening; a second opening forming step of forming a second opening by removing the sacrifice film, after the second insulating film forming step; and a contact plug forming step of forming a contact plug in the second opening.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: November 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Koichi Yatsuda
  • Publication number: 20200152475
    Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.
    Type: Application
    Filed: January 17, 2020
    Publication date: May 14, 2020
    Inventors: Koichi YATSUDA, Takashi HAYAKAWA, Hiroshi OKUNO, Reiji NIINO, Hiroyuki HASHIMOTO, Tatsuya YAMAGUCHI
  • Patent number: 10593556
    Abstract: There is provided a method of fabricating a semiconductor device by performing a process on a substrate, which includes: forming a masking film made of a polymer having a urea bond by supplying polymerizing raw materials to a surface of the substrate on which an etching target film formed; forming an etching pattern on the masking film; subsequently, etching the etching target film with a processing gas using the etching pattern; and subsequently, removing the masking film by heating the substrate to depolymerize the polymer.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Hiroshi Okuno, Reiji Niino, Hiroyuki Hashimoto, Tatsuya Yamaguchi
  • Publication number: 20200035553
    Abstract: A method includes a step of performing a selective catalyst treatment by supplying a catalyst solution to an upper surface of an exposed interconnection layer forming a step portion of a stepped shape formed by pair layers stacked to form the stepped shape, the pair layer including an interconnection layer formed on an insulating layer, and a step of selectively growing a metal layer by performing electroless plating on the upper surface of the interconnection layer on which the catalyst treatment is performed.
    Type: Application
    Filed: February 27, 2018
    Publication date: January 30, 2020
    Inventors: Koichi YATSUDA, Takashi HAYAKAWA, Mitsuaki IWASHITA, Takashi TANAKA
  • Patent number: 10325780
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: supplying a raw material for polymerization to a porous low dielectric constant film formed on a substrate for manufacturing a semiconductor device, and filling holes formed in the porous low dielectric constant film with a polymer having a urea bond; subsequently, forming a pattern mask for etching on a surface of the porous low dielectric constant film; subsequently, etching the porous low dielectric constant film; subsequently, removing the pattern mask; and heating the substrate to depolymerize the polymer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: June 18, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Tatsuya Yamaguchi
  • Publication number: 20190181039
    Abstract: A semiconductor device manufacturing method of forming a trench and a via in a porous low dielectric constant film formed on a substrate as an interlayer insulating film, includes: embedding a polymer having a urea bond in pores of the porous low dielectric constant film by supplying a raw material for polymerization to the porous low dielectric constant film; forming the via by etching the porous low dielectric constant film; subsequently, embedding a protective filling material made of an organic substance in the via; subsequently, forming the trench by etching the porous low dielectric constant film; subsequently, removing the protective filling material; and after the forming a trench, removing the polymer from the pores of the porous low dielectric constant film by heating the substrate to depolymerize the polymer, wherein the embedding a polymer having a urea bond in pores is performed before the forming a trench.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Koichi YATSUDA, Tatsuya YAMAGUCHI, Yannick FEURPRIER, Frederic LAZZARINO, Jean-Francois de MARNEFFE, Khashayar BABAEI GAVAN
  • Publication number: 20190157083
    Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Mitsuaki Iwashita, Takeshi Nagao, Nobutaka Mizutani, Takashi Tanaka, Koichi Yatsuda, Kazutoshi Iwai, Yuichiro Inatomi
  • Publication number: 20190109205
    Abstract: A method for manufacturing a semiconductor device includes: a first insulating film forming step of forming a first insulating film in a transistor having a structure in which a source and a drain raised in a fin shape are covered with a gate; a sacrifice film forming step of forming a sacrifice film; a hard mask pattern forming step of forming a hard mask film having a desired pattern; a first opening forming step of forming a first opening; a second insulating film forming step of forming a second insulating film made of a material different from the first insulating film, in the first opening; a second opening forming step of forming a second opening by removing the sacrifice film, after the second insulating film forming step; and a contact plug forming step of forming a contact plug in the second opening.
    Type: Application
    Filed: June 27, 2016
    Publication date: April 11, 2019
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Koichi YATSUDA
  • Patent number: 10224202
    Abstract: A catalyst is imparted selectively to a plateable material portion 32 by performing a catalyst imparting processing on a substrate W having a non-plateable material portion 31 and the plateable material portion 32 formed on a surface thereof. Then, a hard mask layer 35 is formed selectively on the plateable material portion 32 by performing a plating processing on the substrate W. The non-plateable material portion 31 is made of SiO2 as a main component, and the plateable material portion 32 is made of a material including, as a main component, a material containing at least one of a OCHx group and a NHx group, a metal material containing Si as a main component, a material containing carbon as a main component or a catalyst metal material.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 5, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Mitsuaki Iwashita, Takeshi Nagao, Nobutaka Mizutani, Takashi Tanaka, Koichi Yatsuda, Kazutoshi Iwai, Yuichiro Inatomi
  • Publication number: 20180158693
    Abstract: There is provided a method of manufacturing a semiconductor device, which includes: supplying a raw material for polymerization to a porous low dielectric constant film formed on a substrate for manufacturing a semiconductor device, and filling holes formed in the porous low dielectric constant film with a polymer having a urea bond; subsequently, forming a pattern mask for etching on a surface of the porous low dielectric constant film; subsequently, etching the porous low dielectric constant film; subsequently, removing the pattern mask; and heating the substrate to depolymerize the polymer.
    Type: Application
    Filed: December 5, 2017
    Publication date: June 7, 2018
    Inventors: Koichi Yatsuda, Takashi Hayakawa, Tatsuya Yamaguchi