Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module. The synchronization module includes a receiving section that receives, from each of the plurality of test modules, a state signal indicating a state of the test module; an aggregating section that generates an aggregate state signal by calculating an aggregate of the state signals received by the receiving section; and a transmitting section that transmits, to the plurality of test modules, a control signal ordering an operation corresponding to the aggregate state signal.

Abstract: There is provided a test apparatus for testing a device under test, including: a plurality of test sections; and a first synchronization section and a second synchronization section that, for each of a plurality of domains that respectively include one or more of the plurality of test sections, synchronize the one or more test sections included in the domain, where each of the first synchronization section and the second synchronization section includes: a local collection section that collects, for each domain, synchronization requests from the test sections connected to the corresponding synchronization section; an exchange section that exchanges, for a discrete domain of that includes test sections connected to the first synchronization section and test sections connected to the second synchronization section, synchronization requests collected in the corresponding synchronization section with synchronization requests collected in the other synchronization section; a global collection section that collects

Abstract: There is provided a test apparatus for testing a device under test, including: a plurality of test sections; and a first synchronization section and a second synchronization section that, for each of a plurality of domains that respectively include one or more of the plurality of test sections, synchronize the one or more test sections included in the domain, where each of the first synchronization section and the second synchronization section includes: a local collection section that collects, for each domain, synchronization requests from the test sections connected to the corresponding synchronization section; an exchange section that exchanges, for a discrete domain of that includes test sections connected to the first synchronization section and test sections connected to the second synchronization section, synchronization requests collected in the corresponding synchronization section with synchronization requests collected in the other synchronization section; a global collection section that collects

Abstract: Provided is a test apparatus that tests a device under test, comprising a plurality of test modules that test the device under test; a synchronization module that is connected to each of the plurality of test modules, and that synchronizes the plurality of test modules; and a test control section that is connected to the plurality of test modules and the synchronization module, and that controls the test modules and the synchronization module. The synchronization module includes a receiving section that receives, from each of the plurality of test modules, a state signal indicating a state of the test module; an aggregating section that generates an aggregate state signal by calculating an aggregate of the state signals received by the receiving section; and a transmitting section that transmits, to the plurality of test modules, a control signal ordering an operation corresponding to the aggregate state signal.

Abstract: Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section.

Abstract: Provided is a test apparatus that tests a device under test, comprising a pattern generating section that generates a test pattern for testing the device under test; a signal supplying section that supplies the device under test with a test signal corresponding to the test pattern; a trigger generating section that supplies a trigger signal to an external instrument connected to the device under test; and a synchronization control section that outputs, to the trigger generating section, a synchronization signal instructing generation of the trigger signal, based on at least a portion of the test pattern generated by the pattern generating section.

Abstract: The test apparatus includes: a plurality of test modules that transmit/receive signals to/from the plurality of DUTs; a test head on which the plurality of test modules are placed; a plurality of device interface sections each of which is disposed between the test head and the plurality of test modules, includes a wiring that connects between a connector of the test head connected to the corresponding device under test and the test module and an identification information output section that outputs identification information indicative of the type of the device interface section, and is being capable of exchanging in accordance with the corresponding DUT and test module; and a control device connected to the plurality of test modules that controls the test module. Each test module includes: a reading section that reads the identification information; and a command processing section that returns the identification information to the control device.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply and receive signals to/from the electronic device; a plurality of return circuits operable to receive fail timing signals indicating timing at which a fail occurs on output patterns output from the electronic device, the return circuits being provided corresponding to the plurality of test modules; a plurality of summarizing units operable to receive the fail timing signals output from the plurality of return circuits and compute logical sum of one or more fail timing signals among the plurality of fail timing signals to output one bit signal; and a plurality of distributing units operable to distribute the computed results of corresponding ones of the summarizing units to the plurality of test modules, the distributing units being provided corresponding to the plurality of summarizing units.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation circuit operable to generate timing signals that cause the plurality of test modules to operate based on the reference clock; a plurality of timing sources being provided in response to the plurality of test modules and operable to supply the timing signals to the corresponding test modules; and a control unit operable to control phases of the timing signals supplied to each of the test modules by the plurality of timing sources so that timings at which each of the test modules outputs the test patterns according to the timing signals are made to be equal.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply and receive signals to/from the electronic device; a plurality of return circuits operable to receive fail timing signals indicating timing at which a fail occurs on output patterns output from the electronic device, the return circuits being provided corresponding to the plurality of test modules; a plurality of summarizing units operable to receive the fail timing signals output from the plurality of return circuits and compute logical sum of one or more fail timing signals among the plurality of fail timing signals to output one bit signal; and a plurality of distributing units operable to distribute the computed results of corresponding ones of the summarizing units to the plurality of test modules, the distributing units being provided corresponding to the plurality of summarizing units.

Abstract: There is provided a test apparatus that tests an electronic device. The test apparatus includes: a plurality of test modules operable to supply test patterns used for a test of the electronic device to the electronic device; a reference clock generation unit operable to generate a reference clock; a generation circuit operable to generate timing signals that cause the plurality of test modules to operate based on the reference clock; a plurality of timing sources being provided in response to the plurality of test modules and operable to supply the timing signals to the corresponding test modules; and a control unit operable to control phases of the timing signals supplied to each of the test modules by the plurality of timing sources so that timings at which each of the test modules outputs the test patterns according to the timing signals are made to be equal.