Patents by Inventor Koichiro Aoki
Koichiro Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220201945Abstract: An air conditioning system for mushroom cultivation according to an embodiment includes an air passageway (10) having an intake opening for taking air thereinto, and a supply opening connected to a cultivation chamber (100) for cultivating a mushroom; a temperature control apparatus (20) that controls a temperature of air flowing through the air passageway (10), and a return passageway (30) for returning air in the cultivation chamber (100) to the air passageway (10) between the intake opening and a position at which the temperature control apparatus (20) controls air in temperature.Type: ApplicationFiled: April 23, 2020Publication date: June 30, 2022Applicant: SHINWA CONTROLS CO., LTDInventors: Syunji YAMAGUCHI, Koichiro AOKI, Kenji NISHIMURA
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Patent number: 8922029Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: GrantFiled: February 1, 2012Date of Patent: December 30, 2014Assignee: PS4 Luxco S.A.R.L.Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Publication number: 20120127675Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: ApplicationFiled: February 1, 2012Publication date: May 24, 2012Applicant: ELPIDA MEMORY, INC.Inventors: ATSUSHI HIRAISHI, TOSHIO SUGANO, MASAHIRO YAMAGUCHI, YOJI NISHIO, TSUTOMU HARA, KOICHIRO AOKI
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Patent number: 8134239Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: GrantFiled: September 29, 2008Date of Patent: March 13, 2012Assignee: Elpida Memory, Inc.Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Patent number: 7768867Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: GrantFiled: June 12, 2007Date of Patent: August 3, 2010Assignee: Elpida Memory, Inc.Inventors: Yoji Nishio, Yutaka Uematsu, Seiji Funaba, Hideki Osaka, Tsutomu Hara, Koichiro Aoki
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Publication number: 20090086522Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.Type: ApplicationFiled: September 29, 2008Publication date: April 2, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Atsushi HIRAISHI, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki
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Publication number: 20070291557Abstract: Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.Type: ApplicationFiled: June 12, 2007Publication date: December 20, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Yoji NISHIO, Yutaka UEMATSU, Seiji FUNABA, Hideki OSAKA, Tsutomu HARA, Koichiro AOKI
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Publication number: 20060249829Abstract: A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.Type: ApplicationFiled: April 7, 2006Publication date: November 9, 2006Inventors: Mitsuaki Katagiri, Masanori Shibamoto, Tsutomu Hara, Koichiro Aoki, Naoya Kanda, Shuji Kikuchi, Hisashi Tanie
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Patent number: 4165711Abstract: A fish-gathering block comprising a plurality of supports erected on a base frame and supporting an upper structure. The current flows through an opening between the lower end of the upper structure and the base frame. This flowthrough opening prevents the sinking of the fish-gathering block into the sea-bottom by eliminating or materially weakening the ocean-current's excavating action.Type: GrantFiled: June 1, 1977Date of Patent: August 28, 1979Inventor: Koichiro Aoki