Abstract: A wireless communication apparatus supports a first scheme and a second scheme. A communication range for the second scheme is narrower than a communication range for the first scheme. Processing circuitry of the apparatus is configured to set first information and second information. If the second scheme is used, the processing circuitry sets a second level greater than a first level for the second information and sets a second power value smaller than a first power value for the first information. The first level and the first power value are used for the first scheme. The second power value is decided based on a receiving sensitivity required for a physical scheme selected by the second scheme.

Abstract: An arithmetic device includes storage, a controller, and operation circuitry. The storage stores therein P-dimensional input vectors, P×N-dimensional matrixes, N-dimensional intermediate value vectors, and N-dimensional output vectors, and is capable of executing, in parallel, two or more of reading processing of the input vector, reading processing of the matrix, reading processing of the intermediate value vector, and writing processing of the output vector. The controller sets read timings of a first input vector, a first matrix, and a first intermediate value vector, and write timing of a first output vector, in operation processing including a D-dimensional processing loop. The operation circuitry calculates product of the first input vector and the first matrix, calculates sum of the product and the first intermediate value vector, and stores the sum as the first output vector in the storage.

Abstract: A computing device includes processing circuitry and control circuitry. The processing circuitry computes an M×K-dimensional first output matrix being a product of an M×P-dimensional first input matrix and a P×K-dimensional second input matrix, computes an M×K-dimensional cumulative addition matrix by adding a first output matrix and an M×K-dimensional matrix to store the M×K-dimensional cumulative addition matrix in a cumulative register, compute an addition vector by adding each of M-dimensional cumulative addition vectors included in the cumulative addition matrix and an M-dimensional temporary vector to store the addition vector in each vector register, and output the temporary vector from an M-th one of the vector registers, and perform a vector operation to the output temporary vector to output an output vector. The control circuitry controls the computation instructions as to the computations.

Abstract: A wireless communication apparatus supports a first scheme and a second scheme. A communication range for the second scheme is narrower than a communication range for the first scheme. Processing circuitry of the apparatus is configured to set first information and second information. If the second scheme is used, the processing circuitry sets a second level greater than a first level for the second information and sets a second power value smaller than a first power value for the first information. The first level and the first power value are used for the first scheme. The second power value is decided based on a receiving sensitivity required for a physical scheme selected by the second scheme.

Abstract: A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.

Abstract: A wireless communication apparatus supports a first scheme and a second scheme. A communication range for the second scheme is narrower than a communication range for the first scheme. Processing circuitry of the apparatus is configured to set first information and second information. If the second scheme is used, the processing circuitry sets a second level greater than a first level for the second information and sets a second power value smaller than a first power value for the first information. The first level and the first power value are used for the first scheme. The second power value is decided based on a receiving sensitivity required for a physical scheme selected by the second scheme.

Abstract: A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.

Abstract: An arithmetic device includes storage, a controller, and operation circuitry. The storage stores therein P-dimensional input vectors, P×N-dimensional matrixes, N-dimensional intermediate value vectors, and N-dimensional output vectors, and is capable of executing, in parallel, two or more of reading processing of the input vector, reading processing of the matrix, reading processing of the intermediate value vector, and writing processing of the output vector. The controller sets read timings of a first input vector, a first matrix, and a first intermediate value vector, and write timing of a first output vector, in operation processing including a D-dimensional processing loop. The operation circuitry calculates product of the first input vector and the first matrix, calculates sum of the product and the first intermediate value vector, and stores the sum as the first output vector in the storage.

Abstract: A wireless communication apparatus supports a first scheme and a second scheme. A communication range for the second scheme is narrower than a communication range for the first scheme. Processing circuitry of the apparatus is configured to set first information and second information. If the second scheme is used, the processing circuitry sets a second level greater than a first level for the second information and sets a second power value smaller than a first power value for the first information. The first level and the first power value are used for the first scheme. The second power value is decided based on a receiving sensitivity required for a physical scheme selected by the second scheme.

Abstract: A wireless communication apparatus supports at least a second wireless communication scheme between a first wireless communication scheme and the second wireless communication scheme. The first wireless communication scheme requires that a wireless medium is determined to be busy when a reception level is equal to or greater than a minimum reception sensitivity level of a physical scheme. The apparatus includes first and second processing units. The first processing unit is configured to set a value lower than a maximum transmission power of the first wireless communication scheme, for a maximum transmission power of the second wireless communication scheme and set a value greater than the minimum reception sensitivity level of the physical scheme, for a carrier sense level, when the second wireless communication scheme is used. The second processing unit is configured to carry out carrier sense using the carrier sense level.

Abstract: A wireless communication apparatus supports at least a second wireless communication scheme between a first wireless communication scheme and the second wireless communication scheme. The first wireless communication scheme requires that a wireless medium is determined to be busy when a reception level is equal to or greater than a minimum reception sensitivity level of a physical scheme. The apparatus includes first and second processing units. The first processing unit is configured to set a value lower than a maximum transmission power of the first wireless communication scheme, for a maximum transmission power of the second wireless communication scheme and set a value greater than the minimum reception sensitivity level of the physical scheme, for a carrier sense level, when the second wireless communication scheme is used. The second processing unit is configured to carry out carrier sense using the carrier sense level.

Abstract: A wireless communication apparatus supports at least a second wireless communication scheme between a first wireless communication scheme and the second wireless communication scheme. The first wireless communication scheme requires that a wireless medium is determined to be busy when a reception level is equal to or greater than a minimum reception sensitivity level of a physical scheme. The apparatus includes a first processing unit and a second processing unit. The first processing unit is configured to set a value lower than a maximum transmission power of the first wireless communication scheme, for a maximum transmission power of the second wireless communication scheme and set a value greater than the minimum reception sensitivity level of the physical scheme, for a carrier sense level, when the second wireless communication scheme is used. The second processing unit is configured to carry out carrier sense using the carrier sense level.

Abstract: According to one embodiment, an arithmetic circuit includes follows. The arithmetic unit performs an arithmetic operation including addition and multiplication to generate a first value of (n+m) bits. The rounding preprocessor performs an OR operation on lower (m?k) bits of the first value to generate a second value of 1 bit. The register stores a third value of (n+k+1) bits obtained by concatenating upper (n+k) bits of the first value and the second value. The rounding postprocessor calculates a carry bit value of 1 bit from a most significant bit of the third value and lower (k+1) bits of the third value, and adds the carry bit value to upper n bits of the third value.

Abstract: A wireless communication apparatus supports at least a second wireless communication scheme between a first wireless communication scheme and the second wireless communication scheme. The first wireless communication scheme requires that a wireless medium is determined to be busy when a reception level is equal to or greater than a minimum reception sensitivity level of a physical scheme. The apparatus includes a first processing unit and a second processing unit. The first processing unit is configured to set a value lower than a maximum transmission power of the first wireless communication scheme, for a maximum transmission power of the second wireless communication scheme and set a value greater than the minimum reception sensitivity level of the physical scheme, for a carrier sense level, when the second wireless communication scheme is used. The second processing unit is configured to carry out carrier sense using the carrier sense level.

Abstract: According to one embodiment, a wireless communication apparatus includes a generation unit, a control unit, a transmission unit, a reception unit and an analysis unit. The control unit sets, as a first value, a magnitude of a transmission power of the first frame, and sets, as a second value smaller than the first value, a magnitude of a transmission power of the second frame. The transmission unit transmits the first frame at a first time interval until an acknowledgement frame is received, and transmits the second frame at a second time interval until an accept frame is received. The analysis unit analyzes the request transmission power information. The control unit determines a transmission power of a data frame based on the request transmission power information.

Abstract: A wireless communication apparatus supports at least a second wireless communication scheme between a first wireless communication scheme and the second wireless communication scheme. The first wireless communication scheme requires that a wireless medium is determined to be busy when a reception level is equal to or greater than a minimum reception sensitivity level of a physical scheme. The apparatus includes a first processing unit and a second processing unit. The first processing unit is configured to set a value lower than a maximum transmission power of the first wireless communication scheme, for a maximum transmission power of the second wireless communication scheme and set a value greater than the minimum reception sensitivity level of the physical scheme, for a carrier sense level, when the second wireless communication scheme is used. The second processing unit is configured to carry out carrier sense using the carrier sense level.

Abstract: According to one embodiment, a wireless communication apparatus includes a determination unit, a first setting unit, a second setting unit and a wireless unit. The determination unit determines whether a signal degradation degree is higher than a threshold value. The first setting unit sets first parameters relating to a first data rate and a first communication robustness. The second setting unit sets second parameters relating to a second data rate and a second communication robustness if an instruction signal is received and if the signal degradation degree is higher than the threshold value. The wireless unit communicates with a communication partner using one of the first parameters and the second parameters.

Abstract: According to one embodiment, a transmitting device includes a wireless transmitting unit which wirelessly transmits data. The transmitting device includes a wireless receiving unit which receives the data wirelessly transmitted by the wireless transmitting unit. The transmitting device includes a synchronization signal outputting unit which outputs a synchronization signal to a signal transmitting medium of an electric conductor. The transmitting device includes a synchronization outputting unit which receives the synchronization signal from the signal transmitting medium and outputs a signal including the data received by the wireless receiving unit according to the synchronization signal.

Abstract: An information processor has a CIR estimator configured to estimate channel impulse response of an input signal including a channel estimation sequence and a data sequence, based on the channel estimation sequence, an extended CIR calculator configured to calculate extended channel impulse response based on the channel impulse response estimated by the CIR estimator so that an extended CIR element padded with zeros is repeated a plurality of times in the extended channel impulse response, a Fourier transformer configured to convert the data sequence of the input signal into a frequency domain signal to calculate frequency response based on the extended channel impulse response, and an equalizer configured to perform equalization for removing a distortion from a propagation channel, based on the frequency domain signal and the frequency response.

Abstract: According to one embodiment, a Reed-Solomon decoder comprises an analyzer and a calculator. The analyzer analyzes a data frame and calculates a size of a last code word located at an end of a data portion, using information included in a header portion. The calculator calculates correction coefficients, using the size of the last code word, for correcting coefficients of an error locator polynomial and coefficients of an error value polynomial for the last code word in accordance with a difference between a base size of Reed-Solomon code words and the size of the last code word, before error detection for a code word located immediately before the last code word in the data portion begins.