Patents by Inventor Koichiro Fujita

Koichiro Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11565688
    Abstract: A control device is provided, which includes: a destination determining unit configured to determine a destination of a hybrid vehicle that includes an engine, a motor and a battery and is able to supply waste heat from the engine to the battery; a arrival judging unit configured to judge whether the hybrid vehicle can arrive at the destination with a remaining capacity of the battery based on the remaining capacity and a temperature of the battery; and a vehicle control unit configured to control the hybrid vehicle to start the engine and supply the waste heat from the engine to the battery when the arrival judging unit judges that the hybrid vehicle cannot arrive at the destination.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: January 31, 2023
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Masashi Eto, Koichiro Fujita
  • Publication number: 20210253079
    Abstract: A control device is provided, which includes: a destination determining unit configured to determine a destination of a hybrid vehicle that includes an engine, a motor and a battery and is able to supply waste heat from the engine to the battery; a arrival judging unit configured to judge whether the hybrid vehicle can arrive at the destination with a remaining capacity of the battery based on the remaining capacity and a temperature of the battery; and a vehicle control unit configured to control the hybrid vehicle to start the engine and supply the waste heat from the engine to the battery when the arrival judging unit judges that the hybrid vehicle cannot arrive at the destination.
    Type: Application
    Filed: January 27, 2021
    Publication date: August 19, 2021
    Inventors: Masashi ETO, Koichiro FUJITA
  • Publication number: 20210013879
    Abstract: A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.
    Type: Application
    Filed: July 4, 2020
    Publication date: January 14, 2021
    Inventors: HIROKI KANAI, TOMOTOSHI SATOH, KOICHIRO FUJITA, KENICHI TANAKA, HIROYUKI KOMEDA, NAOMICHI FUJII
  • Patent number: 10892748
    Abstract: A power module includes a power circuit which includes one or more power semiconductors; and a control circuit which supplies a gate signal to each of the one or more power semiconductors. The control circuit includes one or more gate drivers which generate the gate signal in accordance with a control signal and in which a side to which the control signal is input and a side on which the gate signal is generated are insulated, a control input circuit to which the control signal is input and which supplies the control signal to the one or more gate drivers, and a control output circuit which supplies the gate signal to each of the power semiconductors.
    Type: Grant
    Filed: July 4, 2020
    Date of Patent: January 12, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hiroki Kanai, Tomotoshi Satoh, Koichiro Fujita, Kenichi Tanaka, Hiroyuki Komeda, Naomichi Fujii
  • Patent number: 10848144
    Abstract: A switching control circuit that controls on/off of a switching element is provided to efficiently disperse EMI noise due to high-speed switching, the switching control circuit includes a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: November 24, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Akihiro Nishigaki, Koichiro Fujita, Kenichi Tanaka, Tsuyoshi Nakahira
  • Patent number: 10756011
    Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tomotoshi Satoh, Hiroyuki Komeda, Kenichi Tanaka, Koichiro Fujita
  • Publication number: 20200177175
    Abstract: [Object] To efficiently disperse EMI noise due to high-speed switching. [Solution] A switching control circuit that controls on/off of a switching element comprises a gate driver, a variable capacitance element connected to a gate of the switching element, and a capacitance changing circuit that randomly changes a capacitance of the variable capacitance element.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Inventors: AKIHIRO NISHIGAKI, KOICHIRO FUJITA, KENICHI TANAKA, TSUYOSHI NAKAHIRA
  • Patent number: 10648054
    Abstract: A method for producing high-strength galvanized steel sheets having excellent coating adhesion, workability and appearance. The method comprises hot rolling a slab comprising, by mass %, C: 0.05 to 0.30%, Si: 0.1 to 2.0% and Mn: 1.0 to 4.0%, then coiling the steel sheet into a coil at a specific temperature TC, and pickling the steel sheet, cold rolling the hot-rolled steel sheet resulting from the hot rolling, annealing the cold-rolled steel sheet resulting from the cold rolling under specific conditions, and galvanizing the annealed sheet resulting from the annealing in a galvanizing bath containing 0.12 to 0.22 mass % Al.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 12, 2020
    Assignee: JFE STEEL CORPORATION
    Inventors: Yoichi Makimizu, Yoshitsugu Suzuki, Hideyuki Takahashi, Gentaro Takeda, Koichiro Fujita
  • Patent number: 10544477
    Abstract: A method for manufacturing a high-strength galvanized steel sheet includes performing hot rolling, cold rolling, first annealing, pickling, and second annealing. The first annealing is performed to obtain a steel sheet having a steel microstructure including ferrite in an amount of 10% or more and 60% or less in terms of area ratio, and martensite, bainite, and retained austenite in a total amount of 40% or more and 90% or less in terms of area ratio. The second annealing includes heating to an annealing temperature of 750° C. or higher and 850° C. or lower, holding at the annealing temperature for 10 seconds or more and 500 seconds or less, cooling at an average cooling rate of 1° C./s or more and 15° C./s or less, performing a galvanizing treatment, and cooling to a temperature of 150° C. or lower at an average cooling rate of 5° C./s or more and 100° C./s or less.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: January 28, 2020
    Assignee: JFE Steel Corporation
    Inventors: Hideyuki Kimura, Koichiro Fujita, Hiroshi Hasegawa, Mai Aoyama
  • Patent number: 10422015
    Abstract: Provided are a high-strength galvanized steel sheet containing 0.12% to 0.25% C, 0.01% to 1.00% Si, 1.5% to 4.0% Mn, 0.100% or less P, 0.02% or less S, 0.01% to 0.10% Al, 0.001% to 0.010% N, 0.005% to 0.100% Ti, and 0.0005% to 0.0050% B, the remainder being Fe and inevitable impurities, Ti>4N being satisfied. The high-strength galvanized steel sheet contains 80% to 100% martensite in terms of area fraction, 5% or less (including 0%) polygonal ferrite in terms of area fraction, and less than 3% (including 0%) retained austenite in terms of area fraction. The average hardness of martensite is 400 to 500 in terms of Vickers hardness (Hv). The average grain size of martensite is 20 ?m or less. The standard deviation of the grain size of martensite is 7.0 ?m or less.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 24, 2019
    Assignee: JFE Steel Corporation
    Inventors: Hiroshi Hasegawa, Koichiro Fujita
  • Patent number: 10400300
    Abstract: A high-strength hot-dip galvanized steel sheet and a method for manufacturing the steel sheet are provided. The high-strength hot-dip galvanized steel sheet has a specific composition including C, Si, Mn, etc. In this chemical composition, the content of Ti [Ti] and the content of N [N] satisfy [Ti]>4[N]. The high-strength hot-dip galvanized steel sheet has a microstructure including martensite at an area fraction of 60% or more and 90% or less, polygonal ferrite at an area fraction of more than 5% and 40% or less, and retained austenite at an area fraction of less than 3% (including 0%). The average hardness of the martensite is 450 or more and 600 or less in terms of Vickers hardness, and the average crystal grain diameter of the martensite is 10 ?m or less. The standard deviation of the crystal grain diameters of the martensite is 4.0 ?m or less.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 3, 2019
    Assignee: JFE STEEL CORPORATION
    Inventors: Hiroshi Hasegawa, Koichiro Fujita
  • Patent number: 10381472
    Abstract: In a nitride-semiconductor field-effect transistor, an end on a recess side of a first insulating film is separated by a distance from an opening edge of the recess and an end on a recess side of a second insulating film is separated by a distance from the end on the recess side of the first insulating film. A part of a drain electrode out of the recess stretches toward a gate electrode side in an eaves shape, is formed over surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film from the recess, and contacts the surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka Nakayama, Junichiroh Koyama, Koichiro Fujita
  • Publication number: 20190157971
    Abstract: A power supply circuit includes a first switch that is a FET composed of a GaN-based semiconductor material and a second switch that is another FET composed of a GaN-based semiconductor material. The drain of the first switch is connected to an input voltage side, the source of the first switch is connected to the drain of the second switch and an output voltage side. An false-turn-on suppression circuit that hinders, when one of the first switch and the second switch is switched on, the other of the first switch and the second switch from being switched on is connected to the gate of the first switch and/or the gate of the second switch.
    Type: Application
    Filed: November 13, 2018
    Publication date: May 23, 2019
    Inventors: KOICHIRO FUJITA, KENICHI TANAKA, TOMOTOSHI SATOH
  • Patent number: 10294542
    Abstract: A method is provided for producing a high-strength galvanized steel sheet having a microstructure that contains martensite in an area proportion of 20% or more and 60% or less and ferrite in an area proportion of 40% or more and 80% or less includes, in sequence, hot-rolling a steel slab containing a specific component composition, performing cold rolling, performing primary annealing, performing pickling, performing secondary annealing, and performing galvanizing treatment, in which in the primary annealing, heating is performed at an average heating rate of 0.1° C./sec. or more and less than 3° C./sec. in the temperature range of 600° C. to 750° C., an annealing temperature of 750° C. to 850° C. is maintained for 10 to 500 seconds, and then cooling is performed from the annealing temperature range to a cooling stop temperature of 600° C. or lower at an average cooling rate of 1 to 15° C./sec, in which in the pickling, the pickling weight loss of the steel sheet is 0.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 21, 2019
    Assignee: JFE STEEL CORPORATION
    Inventors: Hideyuki Kimura, Koichiro Fujita, Hiroshi Hasegawa
  • Publication number: 20190148281
    Abstract: In a power semiconductor module, a first conductive layer including first to fourth electrodes are formed on one of principal surfaces of an insulating layer, and a conductive substrate functioning as a second conductive layer is formed on the other one of principal surfaces. Current paths are switched by controlling switching of a first transistor and a second transistor disposed on a surface of the first conductive layer thereby performing a power conversion. A capacitor is connected, in a region, between the first electrode and the second electrode. When a current flows in the region through the second conductive layer, a charging/discharging current occurs in the capacitor, which results in magnetic field cancellation.
    Type: Application
    Filed: November 12, 2018
    Publication date: May 16, 2019
    Inventors: TOMOTOSHI SATOH, HIROYUKI KOMEDA, KENICHI TANAKA, KOICHIRO FUJITA
  • Patent number: 9920394
    Abstract: A bake-hardening galvanized steel sheet having a base steel sheet and a coating layer formed on the base steel sheet, the base steel sheet having a specified chemical composition and a metallographic structure including a ferrite phase and a cementite phase, in which an average ferrite grain diameter is controlled to be 10 ?m or more and 30 ?m or less, and in which the surface area of the interface between ferrite and cementite per unit volume is controlled to be 1.0/mm or more and 10.0/mm or less, a hydrogen concentration in steel of the base steel sheet is controlled to be less than 0.1 ppm, and a zinc coating weight per unit surface area of the steel sheet is controlled to be 40 g/m2 or more and 100 g/m2 or less.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: March 20, 2018
    Assignee: JFE STEEL CORPORATION
    Inventors: Kohei Hasegawa, Koichiro Fujita, Yusuke Kimata, Kozo Harada
  • Publication number: 20180040726
    Abstract: In a nitride-semiconductor field-effect transistor, an end on a recess side of a first insulating film is separated by a distance from an opening edge of the recess and an end on a recess side of a second insulating film is separated by a distance from the end on the recess side of the first insulating film. A part of a drain electrode out of the recess stretches toward a gate electrode side in an eaves shape, is formed over surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film from the recess, and contacts the surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 8, 2018
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka NAKAYAMA, Junichiroh KOYAMA, Koichiro FUJITA
  • Patent number: 9828648
    Abstract: A steel sheet and a method for producing the same are disclosed. The steel sheet has a composition containing 0.015% to 0.05% C, less than 0.10% Si, 0.1% to 2.0% Mn, 0.20% or less P, 0.1% or less S, 0.01% to 0.10% Al, 0.005% or less N, and 0.06% to 0.5% Ti in percent by mass, C and Ti satisfying the inequality Ti*/C?4, where Ti* (mass percent)=Ti?3.4N and Ti, C, and N represent the content (mass percent) of each element. The steel sheet has a microstructure which contains a ferrite phase as a base, in which the average grain diameter of the ferrite phase is 7 ?m or more, and in which the ratio of the rolling-direction average grain diameter to thickness-wise average grain diameter of the ferrite phase is 1.1 or more.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 28, 2017
    Assignee: JFE STEEL CORPORATION
    Inventors: Taro Kizu, Koichiro Fujita
  • Patent number: 9824887
    Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si—H bonds equal to or less than 6.0×1021 cm?3, and is formed of silicon nitride.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: November 21, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshimi Tanimoto, Koichiro Fujita, Yushi Inoue, Takao Kinoshita
  • Publication number: 20170301535
    Abstract: A nitride semiconductor device includes a substrate; a nitride semiconductor multilayer structure which is formed on the substrate, includes a first nitride semiconductor layer and a second nitride semiconductor layer having a different composition from that of the first nitride semiconductor layer, and generates two dimensional electron gas on a hetero interface between the first nitride semiconductor layer and the second nitride semiconductor layer; and an insulating film which covers at least a portion of a surface of the nitride semiconductor multilayer structure, has a concentration of Si—H bonds equal to or less than 6.0×1021 cm?3, and is formed of silicon nitride.
    Type: Application
    Filed: August 27, 2015
    Publication date: October 19, 2017
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yoshimi TANIMOTO, Koichiro FUJITA, Yushi INOUE, Takao KINOSHITA