Patents by Inventor Koichiro Hayashida

Koichiro Hayashida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8888913
    Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: November 18, 2014
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
  • Publication number: 20120015454
    Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: January 19, 2012
    Inventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
  • Patent number: 8021484
    Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: September 20, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida
  • Patent number: 7993452
    Abstract: A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer is provided. For example, the method comprises: a pre-cleaning process for cleaning the silicon wafer having top and bottom faces processed to a mirror finish; and a rapid thermal process or an epitaxial growth process, wherein the pre-cleaning process comprises a hydrofluoric acid (HF) process and a subsequent pure water (DIW) process.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Sumco Techxiv Corporation
    Inventors: Koichiro Hayashida, Kazuhiro Narahara, Hirotaka Kato
  • Publication number: 20070228524
    Abstract: A role of a bottom face of a silicon wafer is identified in a manufacturing process of the silicon wafer. And preferable characteristic feature is also identified. In order to obtain the above characteristic feature, a process method to be implemented into the method of manufacturing a normal silicon wafer is provided. For example, the method comprises: a pre-cleaning process for cleaning the silicon wafer having top and bottom faces processed to a mirror finish; and a rapid thermal process or an epitaxial growth process, wherein the pre-cleaning process comprises a hydrofluoric acid (HF) process and a subsequent pure water (DIW) process.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Inventors: Koichiro Hayashida, Kazuhiro Narahara, Hirotaka Kato
  • Publication number: 20070227441
    Abstract: A method of forming an epitaxial layer to increase flatness of an epitaxial silicon wafer is provided. In particular, a method of controlling the epitaxial layer thickness in a peripheral part of the wafer is provided. An apparatus for manufacturing an epitaxial wafer by growing an epitaxial layer with reaction of a semiconductor wafer and a source gas in a reaction furnace comprising: a pocket in which the semiconductor wafer is placed; a susceptor fixing the semiconductor; orientation-dependent control means dependent on a crystal orientation of the semiconductor wafer and/or orientation-independent control means independent from the crystal orientation of the semiconductor wafer, wherein the apparatus may improve flatness in a peripheral part of the epitaxial layer.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 4, 2007
    Inventors: Kazuhiro Narahara, Hirotaka Kato, Koichiro Hayashida